We claim:
1. A cohesive soy-based machineable dough comprising:
dry ingredients including:
a soy component comprising from about 60% to about 90% by weight, of the dry ingredients; and
a pre-gelatinized starch comprising from about 10% to about 40%, by weight, of the dry ingredients; and
wet ingredients including water comprising from about 25% to about 45% by weight of the dough.
2. The cohesive soy-based dough according to claim 1, wherein the soy component is selected from the group consisting of soy flour, soy meal, soy grits, soy chips, powdered soy protein, soy protein isolates, and mixtures thereof.
3. The cohesive soy-based dough according to claim 2, wherein the soy component comprises from about 70% to about 90%, full-fat soy flour, by weight of the soy component.
4. The cohesive soy-based dough according to claim 3, wherein the soy component comprises from about 10% to about 30%, soy grits, by weight of the soy component.
5. The cohesive soy-based dough according to claim 1, wherein pre-gelatinized starch is selected from the group consisting of pre-gelatinized grain starch, pre-gelatinized tuber starch, pre-gelatinized root starch, pre-gelatinized vegetable starch, pre-gelatinized legume starch, and mixtures thereof.
6. The cohesive soy-based dough according to claim 1 wherein the dry ingredients further comprise a non-soy flour selected from the group consisting of grain flour, vegetable flour, plant flour, legume flour, and mixtures thereof, comprising less than about 30%, by weight, of the dry ingredients.
7. The cohesive soy-based dough according to claim 6, wherein the non-soy flour comprises a pre-gelatinized flour.
8. The cohesive soy-based dough according to claim 1 wherein the dry ingredients further comprise a leavening agent comprising less than about 5%, by weight, of the dry ingredients.
9. The cohesive soy-based dough according to claim 1, wherein the wet ingredients further comprise a milk.
10. The cohesive soy-based dough according to claim 1, wherein the wet ingredients further comprise a milk-substitute.
11. A soy-based product comprising a baked sheeted dough, the dough being prepared by mixing dry ingredients including a soy component and a pre-gelatinized starch with water at a temperature above the gelatinization temperature of the starch, the soy component comprising from about 60% to about 90% by weight of the dry ingredients, the pre-gelatinized starch comprising from about 10% to about 40% by weight of the dry ingredients, and the water comprising from about 25% to about 45% by weight of the dough.
12. The soy-based product according to claim 11, wherein the soy component is selected from the group consisting of soy flour, soy meal, soy grits, soy chips, powdered soy protein, soy protein isolates, and mixtures thereof.
13. The soy-based product according to claim 12, wherein the soy component comprises from about 70% to about 90%, full-fat soy flour, by weight of the soy component.
14. The cohesive soy-based product according to claim 13, wherein the soy component comprises from about 10% to about 30%, soy grits, by weight of the soy component.
15. The soy-based product according to claim 11, wherein the pre-gelatinized starch is selected from the group consisting of pre-gelatinized grain starch, pre-gelatinized tuber starch, pre-gelatinized root starch, pre-gelatinized vegetable starch, pre-gelatinized legume starch, and mixtures thereof.
16. The soy-based product according to claim 11 wherein the dry ingredients further comprise a leavening agent comprising less than about 5%, by weight, of the dry ingredients.
17. The soy-based product according to claim 16 wherein the product is a bread.
18. The soy-based product according to claim 16 wherein the product is a cracker.
19. The soy-based product according to claim 11 wherein the product is a chip.
20. A method of producing a soy-based product comprising:
preparing a dough by combining dry ingredients including a soy component and a pre-gelatinized starch with wet ingredients including water at a temperature sufficient to gelatinize the pre-gelatinized starch, wherein the soy component comprises from about 60% to about 90% by weight of the dry ingredients, the pre-gelatinized starch comprises from about 10% to about 40% by weight of the dry ingredients, and the wet ingredients comprise from about 25% to about 45% by weight of the dough;
sheeting the dough and cutting a dough piece from the dough; and
baking the dough piece.
21. The method according to claim 20 further comprising, after baking, frying the dough piece.
22. The method according to claim 20 wherein the soy component is selected from the group consisting of soy flour, soy meal, soy grits, soy chips, powdered soy protein, soy protein isolates, and mixtures thereof.
23. The method according to claim 20, wherein pre-gelatinized starch is selected from the group consisting of pre-gelatinized grain starch, pre-gelatinized tuber starch, pre-gelatinized root starch, pre-gelatinized vegetable starch, pre-gelatinized legume starch, and mixtures thereof.
24. The method according to claim 20, wherein the dry ingredients further comprise a non-soy flour selected from the group consisting of grain flour, vegetable flour, plant flour, legume flour, and mixtures thereof, comprising less than about 30% by weight of the dry ingredients.
25. The method according to claim 24, wherein the non-soy flour comprises a pre-gelatinized flour.
26. The method according to claim 20, wherein the wet ingredients further comprise a milk.
27. The method according to claim 20, wherein the wet ingredients further comprise a milk substitute.
28. The method according to claim 20, wherein the dry ingredients further comprise a flavoring substance comprising less than about 5%, by weight, of the dry ingredients.
29. The method according to claim 20, wherein the dry ingredients further comprise a leavening agent comprising less than about 5%, by weight, of the dry ingredients.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer-implemented method for designing an emulation chip using a selectable fastpath topology, comprising:
determining, from a circuit design for the emulation chip, an initial fastpath topology comprising a plurality of processors connected in series such that each of the plurality of processors is one of N levels of the initial fastpath topology, N being an integer greater than one; and
reducing, using a computer to process the circuit design, the initial fastpath topology from the N-levels to M-levels, where M is an integer greater than zero and less than N, by changing at least one connection among the plurality of processors such that M processors of the plurality of processors are connected in series and N\u2212M processors of the plurality processors are connected in parallel.
2. The method of claim 1 wherein, the reducing is performed in response to at least one design criterion.
3. The method of claim 2, wherein the design criteria comprises an ability to evaluate data using all of the plurality of processors during a duration of one emulation step of an emulation cycle.
4. The method of claim 1, wherein the reducing further comprises disconnecting a path from an output of at least one of the N\u2212M processors to an input of at least one of the M processors.
5. The method of claim 1, further comprising:
performing a static timing analysis of the circuit design; and
performing the reducing in response to the static timing analysis indicating that the initial fastpath topology having the N levels cannot be performed within an emulation step of an emulation cycle.
6. The method of claim 1, wherein the initial fastpath topology comprises:
a first processor of the plurality of processors having an output coupled to an input of each of N\u22121 processors of the plurality of processors;
a second processor of the plurality of processors having an output coupled to an input of each of N\u22122 processors of the plurality of processors, and not connected to an input of the first processor;
a third processor of the plurality of processors having an output connected to an input of each of N\u22123 processors of the plurality of processors, and not connected to an input of the first or second processor.
7. The method of claim 6, wherein the reducing further comprises:
disconnecting a connection between the output of the first processor and the input of the second processor.
8. The method of claim 7, wherein the disconnecting comprises removal of a multiplexer input in the second processor.
9. A computer-implemented method of designing an emulation chip, comprising:
generating, using a computer, an RTL description of the emulation chip, where the RTL description contains an initial fastpath topology having a plurality of processors connected in series such that each of the plurality of processors is one of N levels of the initial fastpath topology, N being an integer greater than one;
synthesizing the RTL description;
performing a design analysis to determine whether the initial fastpath topology is compliant with at least one design criterion; and
reducing, in response to the initial fastpath topology not being compliant with the at least one design criterion, the initial fastpath topology from the N-levels to M-levels, where M is an integer greater than zero and less than N, by changing at least one connection among the plurality of processors such that M processors of the plurality of processors are connected in series and N\u2212M processors of the plurality processors are connected in parallel.
10. The method of claim 9, wherein the design analysis comprises a static timing analysis.
11. The method of claim 10, wherein the at least one design criterion requires that all of the plurality of processors perform data evaluation within one step of an emulation cycle.
12. The method of claim 9, wherein the reducing further comprises:
disconnecting a connection between an output of at least one processor of the plurality of processors and the input of at least one other processor of the plurality of processors to change a serial connection into a parallel connection.
13. The method of claim 12, wherein disconnecting comprises removal of a multiplexer input.
14. Apparatus for designing an emulation chip, comprising:
means for determining, from a circuit design for the emulation chip, an initial fastpath topology comprising a plurality of processors connected in series such that each of the plurality of processors is one of N levels of the initial fastpath topology, N being an integer greater than one; and
means for reducing the initial fastpath topology from the N-levels to M-levels, where M is an integer greater than zero and less than N, by changing at least one connection among the plurality of processors such that M processors of the plurality of processors are connected in series and N\u2212M processors of the plurality processors are connected in parallel.
15. The apparatus of claim 14, wherein the means for reducing changes a series arrangement of at least two processors of the plurality of processors into a parallel arrangement.
16. The apparatus of claim 14, wherein the means for reducing reduces the initial fastpath topology in response to a design criterion.
17. The apparatus of claim 16, wherein the design criterion comprises an ability of the plurality of processors to evaluate data within one step of an emulation cycle.
18. The apparatus of claim 14, wherein each processor of the plurality of processors comprises an input multiplexer and said means for reducing changes the at least one connection by removing an input to the input multiplexer of at least one processor in the plurality of processors.