1. A switch block realizing the connection between interconnection lines connected thereto and comprising:
at least a switching block connected to the interconnection lines and including at least a buffer stage, wherein the switching block further comprises at least a first transistor stage inserted between a first line of the interconnection lines and an input terminal of the buffer stage and connected to a central node of a second line of the interconnection lines, as well as to a third line of the interconnection lines;
a plurality of transistors connected to the buffer stage; and
a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
2. The switch block according to claim 1, wherein the first transistor stage comprises:
a first transistor of the plurality of transistors inserted between the first line and the input terminal of the buffer stage;
a second transistor inserted between the central node of the second line and the input terminal of the buffer stage; and
a third transistor of the plurality of transistors inserted between the third line and the input terminal of the buffer stage.
3. The switch block according to claim 2, wherein the transistors comprised in the switching block are of the NMOS type.
4. The switch block according to claim 1, wherein the switching block further comprises a second transistor stage inserted between an output terminal of the buffer stage and the third line and connected to the central node of the second line, as well as to the first line.
5. The switch block according to claim 4, wherein the second transistor stage comprises:
a fourth transistor inserted between the first line and the output terminal of the buffer stage;
a fifth transistor inserted between the central node of the second line and the output terminal of the buffer stage; and
a sixth transistor inserted between the third line and the output terminal of the buffer stage.
6. The switch block according to claim 5, wherein the decoding stage comprises a plurality of logic gates having a first and a second input terminal connected, in an alternate way, to a first and to a second SRAM cell of the plurality of SRAM cells and respective output terminals connected to the control terminals of the transistors comprised in the first transistor stage of the switching block, as well as further SRAM cells directly connected to the control terminals of the transistors comprised in the second transistor stage of the switching block.
7. The switch block according to claim 6, wherein the decoding stage comprises a supplementary logic gate having a first and a second input terminal connected to the first and second SRAM cell and an output terminal connected to the control terminal of the pull down transistor.
8. The switch block according to claim 1, wherein the decoding stage comprises a plurality of logic gates having a first and a second input terminal connected, in an alternate way, to the SRAM cells and respective output terminals connected to the control terminals of the transistors comprised in the switching block.
9. The switch block according to claim 8, wherein the decoding stage further comprises a supplementary logic gate having three inputs connected to respective output terminals of three of the logic gates and an output terminal connected to a control terminal of a pull down transistor comprised in the switching block and inserted between an input terminal of the buffer stage and a voltage reference.
10. The switch block according to claim 9, wherein the supplementary logic gate is input connected to output terminals of three of the logic gates in turn connected to control terminals of transistors comprised in a second transistor stage in turn comprised in the switching block and inserted between an output terminal of the buffer stage and the third line and connected to the central node of the second line, as well as to the first line and to the output terminal of the buffer stage.
11. A switch block realizing the connection between interconnection lines connected thereto and comprising:
at least a switching block connected to the interconnection lines and including at least a buffer stage, wherein the switching block further comprises a pull down transistor inserted between an input terminal of the buffer stage and a voltage reference;
a plurality of transistors connected to the buffer stage; and
a decoding stage inserted between a plurality of SRAM cells and respective control terminals of the plurality of transistors of the switching block.
12. The switch block according to claim 11, wherein the pull down transistor has a gate terminal connected to the decoding stage and is driven to connect the input terminal of the buffer stage to the voltage reference in the absence of signals on the input terminal.
13. The switch block according to claim 11, wherein the pull down transistor comprised in the switching block is of the NMOS type.
14. A switch circuit, comprising;
first, second, and third nodes;
six switches for intercoupling the nodes; and
a control circuit coupled to the switches and operable to,
close a first switch coupled to the first node and a second switch coupled to the second node to allow a signal to propagate from the first node to the second node;
close a third switch coupled to the second node and a fourth switch coupled to the first node to allow a signal to propagate from the second node to the first node;
close a fifth switch coupled to the second node and the fourth switch coupled to the third node to allow a signal to propagate from the second node to the third node;
close a sixth switch coupled to the third node and the second switch coupled to the second node to allow a signal to propagate from the third node to the second node;
close the first switch coupled to the first node and the fifth switch coupled to the third node to allow a signal to propagate from the first node to the third node; and
close the third switch coupled to the third node and the sixth switch coupled to the first node to allow a signal to propagate from the third node to the first node.
15. The switch circuit of claim 14, wherein:
the first node is operable to connect to an end point of a first connection line;
the second node is operable to connect to an intermediate point of a second connection line; and
the third node is operable to connect to an end point of a third connection line.
16. The switch circuit of claim 14, wherein the first, second, third, fourth, fifth and sixth switches are coupled such that the signals all propagate through a common buffer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor storage device precharging a bit line pair to a ground potential, the semiconductor storage device comprising:
a sense amplifier connected between the bit line pair;
a storage cell connected to one of the bit line pair and storing data;
a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node;
a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor being controlled from the first transistor; and
a capacitor setting a potential of the reference cell node, wherein
the semiconductor storage device aids charge and discharge of the capacitor when the second transistor is in the conduction state by using a negative-phase current of a current flowing between the reference cell node and the second transistor,
the capacitor is connected between a bias node and the reference cell node and sets the potential of the reference cell node according to a stored charge amount, the bias node being supplied with a bias voltage generated by a bias voltage generating circuit, and
the reference cell node and the bias node are electrically connected when the second transistor is in the conduction state so that the negative-phase current of the current flowing between the reference cell node and the second transistor is generated to aid the charge and the discharge of the capacitor.
2. The semiconductor storage device according to claim 1, wherein the reference voltage source and the bias voltage generating circuit are formed by one power supply circuit.
3. The semiconductor storage device according to claim 1, wherein a wiring resistance between the bias node and the reference cell node is lower than a wiring resistance between the reference cell node and the reference voltage source.
4. The semiconductor storage device according to claim 1, wherein a voltage generated by the bias voltage generating circuit is applied to the other end of the storage cell which is not connected to one of the bit line pair.
5. The semiconductor storage device according to claim 1, further comprising:
a third transistor controlling a conduction state between one of the bit line pair and a second reference cell node;
a fourth transistor connected between the second reference cell node and the second transistor, the fourth transistor being controlled from the third transistor; and
a second capacitor connected to the second reference cell node and setting a potential of the second reference cell node according to the stored charge amount, wherein
the second transistor and the fourth transistor are electrically connected so that the negative-phase current of the current flowing between the first reference cell node and the second transistor is generated to aid the charge and the discharge of the capacitor.
6. The semiconductor storage device according to claim 5, wherein the other end of the second transistor which is not connected to the first reference cell node and the other end of the fourth transistor which is not connected to the second reference cell node are commonly connected to the reference voltage source.
7. The semiconductor storage device according to claim 1, wherein the reference voltage source generates a voltage which is substantially half of a power supply voltage of the semiconductor storage device.
8. A semiconductor storage device precharging a bit line pair to a ground potential, the semiconductor storage device comprising:
a sense amplifier connected between the bit line pair;
a storage cell connected to one of the bit line pair and storing data;
a first transistor controlling a conduction state between the other of the bit line pair and a first reference cell node;
a second transistor connected to the first reference cell node and controlled from the first transistor;
a first capacitor connected to the first reference cell node and setting a potential of the first reference cell node according to a stored charge amount;
a third transistor controlling a conduction state between one of the bit line pair and a second reference cell node;
a fourth transistor connected between the second reference cell node and the second transistor and controlled from the third transistor;
a second capacitor connected to the second reference cell node and setting a potential of the second reference cell node according to a stored charge amount; and
a control circuit selectively controlling a state of electrically connecting to at least one of the first reference cell node and the second reference cell node and a bias node and a state of electrically connecting the second transistor and the fourth transistor when the second transistor and the fourth transistor are in the conduction state.