1-41. (canceled)
42. A method of increasing the utilization efficiency of absorbed light energy in a photosynthetic microorganism incapable of flagella-based motility comprising:
a. transforming the microorganism with an RNAi construct in operable linkage with a light activated promoter, wherein the RNAi construct targets a transcript encoding an antenna protein in the microorganism;
b. culturing the transformed microorganism in a culture container made of non-transparent material;
c. exposing the transformed microorganism to light only from above the plane of the surface of the culture media; and
d. screening the transformed microorganism for the ability to generate more oxygen, lipid, hydrogen, recombinant protein or ATP than a starting strain.
43. A photosynthetic microorganism containing an antisense or RNAi construct that targets a transcript of a gene that encodes a protein involved in light harvesting, wherein the antisense or RNAi construct is in operable linkage with a promoter that is activated by light.
44. A genetic construct comprising:
a. a light activated promoter;
b. an antisense or RNAi segment that contains at least 10 nucleotides of a gene encoding a protein involved in light harvesting; and
c. a screenable or selectable marker gene in operable linkage with a promoter.
45. The genetic construct of claim 44, wherein the antisense or RNAi segment encodes a section of a gene that encodes a protein that binds a light absorbing pigment.
46. A population of photosynthetic microorganisms in liquid culture media, wherein:
a. the population is exposed to light from above the plane of the surface of the culture media;
b. at least one cell in the population contains an antisense or RNAi segment comprising at least 10 nucleotides of a gene encoding a protein involved in light harvesting in operable linkage with a promoter that is activated by light; and
c. cells on the top of the population express the antisense or RNAi segment at a higher level than cells on the bottom of the population.
47. The population of claim 46, wherein the cells of the population are incapable of flagella-based motility.
48. (canceled)
49. The genetic construct of claim 44, wherein the genetic construct comprises an RNAi segment.
50. The genetic construct of claim 49, wherein the RNAi segment targets transcripts from more than one gene.
51. The genetic construct of claim 44, wherein the genetic construct comprises an antisense segment.
52. The genetic construct of claim 51, wherein the antisense segment targets transcripts from more than one gene.
53. (canceled)
54. The genetic construct of claim 49, wherein the RNAi segment targets transcripts from only one gene.
55. The genetic construct of claim 51, wherein the antisense segment targets transcripts from only one gene.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A flash memory device, comprising:
a plurality of memory cell blocks, each memory cell block being associated with select lines, pass word lines, and word lines, at least one pass word line being provided between one select line and one word line;
an operating voltage generator to output operating voltages to global select lines, global word lines and global pass word lines;
a block switching unit to connect the global word lines to the word lines and the select lines in response to a block select signal; and
a voltage supply circuit connected to the select lines and the pass word lines and configured to supply the select lines and the pass word lines with a ground voltage in response to a block select inverse signal.
2. The flash memory device of claim 1, wherein the select lines, the word lines and the pass word lines are formed at a same distance in the memory cell block.
3. The flash memory device of claim 1, wherein the select lines, the word lines and the pass word lines are configured to have substantially the same width.
4. The flash memory device of claim 1, wherein the operating voltage generator comprises:
a select line voltage generator to supply a first voltage to the global select lines;
a programreaderase voltage generator to supply a second voltage to the global word lines; and
a pass voltage generator to supply a third voltage to the global pass word lines.
5. The flash memory device of claim 1, wherein the block switching unit is configured to connect the global pass word lines and the pass word lines in response to the block select signal.
6. The flash memory device of claim 1, wherein the global pass word lines and the pass word lines are connected directly.
7. The flash memory device of claim 1, wherein the voltage supply circuit is provided in each memory cell block.
8. The flash memory device of claim 1, wherein:
the voltage supply circuit includes switching elements configured to operate in response to the block select inverse signal, the switch elements having first ends and second ends, the first ends connected to the select lines and the pass word lines, respectively, the second ends connected to a ground terminal.
9. The flash memory device of claim 1, further comprising a switching unit to connect pass word lines of a block group including two or more of the memory cell blocks to the global pass word line in response to a block group select signal.
10. The flash memory device of claim 9, wherein when the block select signal to select one of the memory cell blocks included in the block group is activated, the block group select signal is activated.
11. A method for programming a NAND flash memory device, the method comprising:
providing a plurality of memory cell blocks, each memory cell block being associated with at least one drain select line, at least one source select line, a plurality of word lines, at least one drain pass word line, and at least one source pass word line, the drain pass word line provided between the drain select line and the word line, the source pass word line provided between the source select line and the word line;
applying a pass voltage to a drain pass word line and a source pass word line associated with a selected memory cell block; and
applying a ground voltage to drain pass word lines and source pass word lines associated with unselected memory cell blocks.
12. The method of claim 11, wherein the drain select line of the selected memory cell block is applied with a power supply voltage, and the source select line of the selected memory cell block is applied with the ground voltage, and
the drain select lines and the source select lines of the unselected memory cell blocks are applied with the ground voltage.
13. The method of claim 12, further comprising:
applying a program voltage to a word line associated with a selected memory cell of the selected memory cell block;
applying the pass voltage to a word line associated with an unselected memory cell of the selected memory cell block; and
floating the word lines associated with the unselected memory cell blocks.
14. A method for reading a NAND flash memory device, the method comprising:
providing a plurality of memory cell blocks, each memory cell block comprising a drain select line, a source select line and word lines, and having a drain pass word line and a source pass word line provided between the drain select line and the word line and between the source select line and the word line, respectively;
applying a read pass voltage to a drain pass word line and a source pass word line of a selected memory cell block; and
applying the read pass voltage or a ground voltage to drain pass word lines and source pass word lines of unselected memory cell.
15. The method of claim 14, the drain select line and the source select line of the selected memory cell block are applied with a power supply voltage, and the drain select lines and the source select lines of the unselected memory cell blocks are applied with a ground voltage.
16. The method of claim 15, further comprising:
applying a read voltage to a word line of a selected memory cell of the selected memory cell block; and
applying the read pass voltage to word lines of unselected memory cells of the selected memory cell block; and
floating word lines of the unselected memory cell.
17. A method for erasing a flash memory device, the method comprising:
providing a plurality of memory cell blocks, each memory cell block comprising a drain select line, a source select line and word lines, and having a drain pass word line and a source pass word line provided between the drain select line and the word line and between the source select line and the word line, respectively;
applying a ground voltage to a drain pass word line and a source pass word line of a selected memory cell block; and
floating drain pass word lines and source pass word lines of unselected memory cell blocks.
18. The method of claim 17, wherein the drain select line and the source select line of the selected memory cell block are set to a floating state, word lines of the selected memory cell block are applied with the ground voltage, and the drain select lines, the source select lines and the word lines of the unselected memory cell blocks are set to a floating state.
19. The method of claim 17, further comprising:
performing a post program operation after the erase operation in order to narrow the threshold voltage distributions of the memory cells erased by the erase operation.
20. The method of claim 19, wherein in the post program operation, the word lines, the drain pass word line and the source pass word line of the selected memory cell block are applied with a post program voltage, the word lines of the unselected memory cell blocks are set to a floating state, and the drain pass word lines and the source pass word lines of the unselected memory cell blocks are applied with the ground voltage.
21. The method of claim 20, wherein:
the drain select lines of the selected memory cell block and the unselected memory cell blocks are applied with a power supply voltage, and
the source select lines of the selected memory cell block and the unselected memory cell blocks are applied with the ground voltage.
22. The method of claim 17, further comprising:
performing an erase verify operation after performing the erase operation.
23. The method of claim 19, further comprising;
performing an erase verify operation after performing the post program operation.