What is claimed is:
1. A reference generator for providing a reference voltage to a data bitline precharged to a first voltage in a folded bitline ferroelectric memory device, comprising:
a ferroelectric reference memory array substantially similar to a data memory array in the memory device;
a reference charging circuit adapted to selectively charge a reference bitline in the reference memory array to a second voltage in a read operation; and
a switching circuit adapted to selectively couple a data bitline precharged to the first voltage in the data memory array with the reference bitline in the reference memory array pre-charged to the second voltage in the read operation to provide a reference voltage on the coupled data and reference bitlines between the first and second voltages.
2. The reference generator of claim 1, wherein the data bitline is coupled with a first integer number of ferroelectric data memory cells in the data memory array, wherein the reference bitline is coupled with a second integer number of ferroelectric reference memory cells in the reference memory array, and wherein the switching circuit is adapted to couple the data bitline and the reference bitline to provide the reference voltage approximately according to a ratio of the second integer number to the sum of first and second integer numbers and according to the difference between the second voltage and the first voltage.
3. The reference generator of claim 2, wherein the switching circuit is adapted to couple the data bitline and the reference bitline to provide the reference voltage approximately according to the first voltage plus the ratio of the second integer number to the sum of the first and second integer numbers times the difference between the second voltage and the first voltage.
4. The reference generator of claim 1, wherein the reference memory array comprises a first set of ferroelectric reference memory cells coupled with a first reference bitline and a second set of ferroelectric reference memory cells coupled with a second reference bitline, wherein the reference charging circuit is adapted to selectively charge the second reference bitline to a second voltage in a read operation in which one of a first set of ferroelectric data memory cells along a first data bitline is being read and to selectively charge the first reference bitline to the second voltage in a read operation in which one of a second set of ferroelectric data memory cells along a second data bitline is being read, and wherein the switching circuit is adapted to selectively couple the second data bitline with the second reference bitline in a read operation in which one of the first set of ferroelectric data memory cells is being read and to couple the first data bitline with the first reference bitline in a read operation in which one of the second set of ferroelectric data memory cells is being read.
5. A semiconductor device, comprising:
a data memory array comprising:
a first set of ferroelectric data memory cells coupled with a first data bitline,
a second set of ferroelectric data memory cells coupled with a second data bitline, and
a data charging circuit adapted to selectively charge the second data bitline to a first voltage in a read operation in which one of the first set of ferroelectric data memory cells is being read and to selectively charge the first data bitline to the first voltage in a read operation in which one of the second set of ferroelectric data memory cells is being read; and a reference memory array comprising:
a first set of ferroelectric reference memory cells coupled with a first reference bitline, wherein the first set of ferroelectric reference memory cells is substantially similar to the first set of ferroelectric data memory cells,
a second set of ferroelectric reference memory cells coupled with a second reference bitline, wherein the second set of ferroelectric reference memory cells is substantially similar to the second set of ferroelectric data memory cells,
a reference charging circuit adapted to selectively charge the second reference bitline to a second voltage in a read operation in which one of the first set of ferroelectric data memory cells is being read and to selectively charge the first reference bitline to the second voltage in a read operation in which one of the second set of ferroelectric data memory cells is being read, and
a switching circuit adapted to selectively couple the second data bitline with the second reference bitline in a read operation in which one of the first set of ferroelectric data memory cells is being read and to couple the first data bitline with the first reference bitline in a read operation in which one of the second set of ferroelectric data memory cells is being read.
6. The device of claim 5, further comprising a sense amp coupled with the first and second data bitlines and adapted to sense a voltage across the first and second data bitlines during a read operation.
7. The device of claim 6, wherein the reference charging circuit is adapted to selectively charge one of the first and second reference bitlines to the second voltage according to a reference charging control signal, wherein the switching circuit is adapted to selectively couple the second data bitline with the second reference bitline or to couple the first data bitline with the first reference bitline according to a switching control signal, wherein the device further comprises a control circuit providing the reference charging control signal to the reference charging circuit and providing a switching control signal to the switching circuit, and wherein the control circuit is adapted to provide the switching control signal after the reference charging control signal.
8. The device of claim 7, wherein the data charging circuit is adapted to selectively charge one of the first and second data bitlines to the first voltage according to a data charging control signal, wherein the control circuit is adapted to provide the data charging control signal to the data charging circuit, and wherein the control circuit is adapted to provide the switching control signal after the reference charging control signal and the data charging signal.
9. The device of claim 8, wherein the switching circuit is adapted during the read operation to selectively couple the first data bitline precharged to the first voltage with the first reference bitline precharged to the second voltage or to couple the second data bitline precharged to the first voltage with the second reference bitline precharged to the second voltage, and wherein a reference voltage on a coupled data bitline and reference bitline equalizes in a read operation to a voltage between the first and second voltages according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.
10. The device of claim 9, wherein the first voltage is about zero volts.
11. The device of claim 10, wherein the second voltage is a supply voltage.
12. The device of claim 9, wherein the second voltage is a supply voltage.
13. The device of claim 6, wherein the switching circuit is adapted during the read operation to selectively couple the first data bitline precharged to the first voltage with the first reference bitline precharged to the second voltage or to couple the second data bitline precharged to the first voltage with the second reference bitline precharged to the second voltage, and wherein a reference voltage on a coupled data bitline and reference bitline equalizes in a read operation to a voltage between the first and second voltages according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.
14. The device of claim 6, wherein the first voltage is about zero volts.
15. The device of claim 5, wherein the switching circuit is adapted during the read operation to selectively couple the first data bitline precharged to the first voltage with the first reference bitline precharged to the second voltage or to couple the second data bitline precharged to the first voltage with the second reference bitline precharged to the second voltage, and wherein a reference voltage on a coupled data bitline and reference bitline equalizes in a read operation to a voltage between the first and second voltages according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.
16. The device of claim 5, wherein the first voltage is about zero volts.
17. The device of claim 5, wherein the reference memory array is substantially similar to the data memory array.
18. The device of claim 5, comprising first and second ferroelectric data memory arrays, wherein the switching circuit is adapted to selectively couple the reference memory array with one of the first and second ferroelectric data memory arrays to provide a reference voltage thereto during a read operation.
19. A method of generating a reference voltage in a semiconductor device for reading at least one ferroelectric data cell, the method comprising:
charging a first data bitline in a ferroelectric data array to a first voltage in a read operation in which a ferroelectric data cell coupled with a second complementary data bitline is to be read;
charging a first reference bitline in a ferroelectric reference array to a second voltage in the read operation, wherein the reference array is substantially similar to the data array; and
coupling the first data bitline with the first reference bitline after charging the first reference bitline and the first data bitline.
20. The method of claim 19, wherein charging the first data bitline comprises coupling the first data bitline to ground in the read operation and wherein charging the first reference bitline comprises coupling the first reference bitline to a supply voltage, further comprising:
decoupling the first data bitline from ground before coupling the first data bitline with the first reference bitline; and
decoupling the first reference bitline from the supply voltage before coupling the first data bitline with the first reference bitline.
21. The method of claim 20, wherein coupling the first data bitline with the first reference bitline comprises equalizing in a read operation to a voltage between the first and second voltages according to a ratio of a number of reference memory cells along the coupled reference bitline to the number of reference memory cells along the coupled reference bitline plus a number of data memory cells along the coupled data bitline.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. Process for the hydrogenation of a polymer composed of diene monomer units and nitrile group containing monomer units, in which the hydrogenation in the form of an aqueous dispersion is carried out in the presence of hydrazine and an oxidizing compound characterized in that crosslinks formed as a result of the hydrogenation are broken by adding after the hydrogenation, a compound that satisfies formula I or by adding before, during or after the hydrogenation a compound that statisties formula II
2
where
R1 is a hydrogen atom, an alkyl or cycloalkyl group with 1-30 carbon atoms, or an aromatic group with 6-30 carbon atoms and R2 is an alkyl or cycloalkyl group with 1-30 carbon atoms, or an aromatic group with 6-30 carbon atoms,
X is chosen from the group comprising R3, OR4, SR4, NR5R6, where R3, R4 and R5 are a hydrogen atom, an alkyl or cycloalkyl group with 1-30 carbon atoms or an aromatic group with 6-30 carbon atoms and R6 is an alkyl or cycloalkyl group with 1-30 carbon atoms or an aromatic group with 6-30 carbon atoms
Y is chosen from the group comprising R7, OR8, SR8, NR9R10 and NCR11R12, where R7, R8, R9, R10, R11, and R12 are a hydrogen atom, an alkyl or cycloalkyl group with 1-30 carbon atoms or an aromatic group with 6-30 carbon atoms, and it being possible for R3-R12 to also contain one or more heteroatoms from the groups 13, 14, 15, 16 or 17 of the Periodic System of the Elements.
2. Process according to claim 1, characterized in that R1 is a hydrogen atom.
3. Process according to claim 2, characterized in that hydroxylamine is used as the compound that satisfies formula I.
4. Process according to claim 3, characterized in that crumb of the hydrogenated polymer is contacted with a 1-10 wt. % solution of hydroxylamine in water.
5. Process according to claim 1, characterized in that use is made of a compound that satisfies formula II with Y being an OH group.
6. Process according to either of claims 1 or 5, characterized in that the compound satisfies formula II with Y being an OH group, R1 a hydrogen atom and R2 an alkyl or cycloalkyl group with 1-15 carbon atoms or an aryl group with 6-10 carbon atoms.
7. Process according to any one of claims 1-6, characterized in that the compound that satisfies formula II, where Y is an OH group, R1 a hydrogen atom and R2 an alkyl or cycloalkyl group with 1-15 carbon atoms or an aryl group with 6-10 carbon atoms, is added before or during the hydrogenation and in that hydroxylamine is added during post-treatment of the hydrogenated polymer crumb.
8. Process according to claim 7, characterized in that the hydrogenated polymer is kneaded at elevated temperature.
9. Process according to claim 8, characterized in that the temperature at which the hydrogenated polymer is kneaded lies between 100 and 200 C.
10. Process according to claims 8-9, characterized in that an o-aromatic diamine is used as the compound that satisfies formula I in combination with a ketone.
11. Polymer composition in solid form that contains hydrogenated polymer composed of diene monomer units and nitrile group containing monomer units, characterized in that the hydrogenated polymer has an peak ratio >1, measured by means of 1H-NMR, the peak having been measured between 2.05 and 2.2 ppm and the peak having been measured between 1.8 and 2.05 ppm, a gel content of less than 15 wt. % and a molecular weight distribution (MwMn, measured using gel permeation chromatography) of the soluble part of the polymer composition of <10.
12. Polymer composition according to claim 11, characterized in that the gel content is less than 10 wt. %.