1. A secure cable housing system for use within a secure fiber optic communications network comprising:
a non-secure cable box comprising:
a plurality of walls defining a non-secure interior cavity, wherein at least one of the walls of the non-secure cable box is moveable between opened and closed positions to provide access to the non-secure interior cavity;
a first opening through one of the walls configured to receive an optical cable into the non-secure interior cavity, wherein the non-secure cable box is configured to support the optical cable; and
a second opening through one of the walls configured to provide access to at least one optical fiber of the optical cable; and
a secure network equipment box comprising:
a bottom wall;
a plurality of sidewalls coupled to the bottom wall, each sidewall having an outer surface and an inner surface;
a moveable wall coupled to the plurality of sidewalls, wherein the bottom wall, the sidewalls and the moveable wall define a secure interior cavity, wherein the moveable wall is moveable between opened and closed positions to provide access to the secure interior cavity, wherein the non-secure cable box is smaller than the secure interior cavity such that the non-secure cable box fits within the secure interior cavity;
a locking mechanism configured to lock the moveable wall of the secure network equipment box in the closed position; and
a slot formed through a first sidewall of the plurality of sidewalls, the slot having an entrance at an edge of the first sidewall and a closed bottom end located within the first sidewall, the slot providing a passage extending between the outer surface and the inner surface of the first sidewall, wherein the slot allows the optical cable to be received through the first sidewall into the secure interior cavity without disconnecting the fiber optic cable from the non-secure box.
2. The secure cable housing system of claim 1 further comprising a plug sized to block a remaining open portion of the slot following receipt of the optical cable through the slot, wherein the plug is configured to be removably coupled to a portion of the inner surface of the first sidewall adjacent the slot to hold the plug in place within the slot.
3. The secure cable housing system of claim 1 wherein the secure network equipment box further comprises:
an opening extending between the outer surface and the inner surface of one of the plurality of sidewalls, the preformed opening configured to provide an exit point for a non-secure optical fiber and a power cable from the secure interior cavity; and
a bracket having an outer surface facing the inner surface of the sidewall having the opening, the outer surface of the bracket and the inner surface of the sidewall defining a channel having a first open end adjacent the opening and a second open end opposite the first open end.
4. The secure cable housing system of claim 3 further comprising an optical network terminal located within the secure interior cavity, wherein the power cable extends from the optical network terminal through the second open end into the channel, out of the channel through the first open end of the channel and out of the secure network equipment box through the opening, wherein the non-secure optical fiber also extends through the second open end into the channel, out of the channel through the first open end of the channel and out of the secure network equipment box through the opening.
5. The secure cable housing system of claim 1 wherein the secure network equipment box further comprises:
an array of outer vent openings extending through at least one of the plurality of sidewalls and the moveable wall; and
a vent panel positioned between the array of outer vent openings and the secure interior cavity.
6. The secure cable housing system of claim 5, wherein the vent panel includes an array of vent panel openings, wherein the vent panel openings are off-set from the array of outer vent openings such that none of the outer vent openings are aligned with the vent panel openings such that there is not a straight path that extends through one of the outer vent openings and through one of the vent panel openings.
7. The secure cable housing system of claim 5 wherein the vent panel is coupled to the inner surface of the at least one sidewall and top wall including the array of outer vent openings such that the vent panel surrounds the array of outer vent openings.
8. The secure cable housing system of claim 1 wherein the optical cable comprises at least two optical fibers, and wherein the optical fibers furcate from the optical cable within the interior cavity of the non-secure cable box, wherein the non-secure cable box includes an adapter located within the second opening of the non-secure cable box and the adapter provides the access to the at least one optical fiber of the optical cable.
9. The secure cable housing system of claim 1 wherein the secure network equipment box further comprises:
a communication interface located within the secure interior cavity, the communication interface including an internal port and an external port, wherein the internal port is configured to receive a cable from an optical network terminal located within the secure interior cavity, wherein the external port is accessible from an exterior of the secure network equipment box to connect to a cable from a user; and
a door moveable between a closed position in which the door blocks access to the external port and an open position in which the access is provided to the external port.
10. The secure cable housing system of claim 9 wherein the locking mechanism is a single lock configured to lock both the door and the top wall.
11. The secure cable housing system of claim 10 wherein the secure network equipment box further comprises:
at least one fastener coupling the top wall to a second sidewall of one of the plurality of sidewalls;
an opening formed through the second sidewall, wherein the external port of the communication interface is accessible through the opening, wherein the door blocks the opening through the second sidewall, the external port and the at least one fastener when in the closed position.
12. A secure network equipment box for use within a fiber optic communications network comprising:
a plurality of walls defining an interior cavity, an outer surface and an inner surface;
at least one communication interface located within the interior cavity, the communication interface including an internal port and an external port, wherein the internal port is configured to receive a cable from an optical network terminal, wherein the external port is accessible from an exterior of the secure network equipment box to receive a cable from a user;
a door moveable between a closed position in which the door blocks access to the external port and an open position in which the access is provided to the external port; and
a locking mechanism configured to lock the door in the closed position.
13. The secure network equipment box of claim 12 wherein one of the plurality of walls is a top wall moveable between opened and closed positions to provide access to the interior cavity, wherein the locking mechanism is a single lock configured to lock both the door and the top wall.
14. The secure network equipment box of claim 13 wherein one of the plurality of walls is a sidewall, the secure network equipment box further comprising:
at least one fastener coupling the top wall to the sidewall; and
an opening formed through the sidewall, wherein the external port of the communication interface is accessible through the opening, wherein the door blocks the opening through the sidewall, the external port and the at least one fastener when in the closed position.
15. The secure network equipment box of claim 12 wherein one of the plurality of walls is a sidewall, the secure network equipment box further comprising a slot formed through the sidewall, the slot having an entrance at an edge of the sidewall and a closed bottom end located within the sidewall, the slot providing a passage extending between the outer surface and the inner surface of the sidewall, wherein the slot allows an optical cable to be received through the sidewall into the secure interior cavity.
16. The secure network equipment box of claim 15 further comprising a plug sized to block a remaining open portion of the slot following receipt of the optical cable through the slot, wherein the plug is configured to be removably coupled to a portion of sidewall adjacent the slot to hold the plug in place within the slot.
17. The secure network equipment box of claim 12 further comprising an optical network terminal located within the interior cavity.
18. A method of converting a non-secure optical network to a secure optical network comprising:
providing an optical cable coupled within a non-secure cable box;
providing a secure network equipment box including:
a plurality of walls defining an interior cavity, an outer surface and an inner surface, wherein one of the walls is a moveable wall moveable between opened and closed positions to provide access to the interior cavity;
a locking mechanism configured to lock the moveable wall in the closed position; and
an opening extending through one of the plurality of walls sized to receive the optical cable; and
mounting the non-secure cable box within the interior cavity of the secure network equipment box such that optical cable extends through the opening without decoupling the non-secure cable box from the optical cable.
19. The method of claim 18 wherein the opening is a slot formed through one of the plurality of walls, the slot having an entrance at an edge of the one of the plurality of walls and a closed bottom end located within the one of the plurality of walls, the method further comprising placing the cable into the slot through the entrance and positioning the cable adjacent the closed bottom end.
20. The method of claim 19 further comprising:
inserting a plug into the slot such that a first end of the plug is positioned adjacent the optical cable and a second end of the plug is substantially coplanar with the edge of the one of the plurality of walls; and
coupling the plug to the inner surface of one of the plurality of walls adjacent the slot.
21. The method of claim 20 further comprising:
closing the moveable wall to the closed position with the non-secure cable box within the interior cavity; and
locking the movable wall in the closed position.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A voltage regulator for a bit line of a semiconductor memory, comprising:
a reference voltage source providing an output voltage at a substantially constant voltage;
a feedback transistor; and
a voltage-stabilized inverter comprising:
a first input connected to the bit line and to a source of the feedback transistor;
a second input connected to the substantially constant voltage;
an output connected to a gate of the feedback transistor to regulate a voltage on the bit line;
an inverter transistor;
a current source transistor parallel to the inverter transistor; and
a current mirror between an operating voltage and the inverter transistor.
2. The voltage regulator according to claim 1,
wherein the inverter transistor comprises an inverter gate, an inverter source, and inverter drain, wherein the inverter gate is connected to the first input, the inverter drain is connected to the output and the inverter source is at ground.
3. The voltage regulator according to claim 2 wherein the current source transistor and the inverter transistor are identical, so that the output voltage of the reference voltage source adjusts itself at the inverter gate of the inverter transistor.
4. A sense amplifier for reading out the state of a semiconductor memory cell via a bit line, comprising:
a first voltage regulator according to claim 1, wherein a first input of a voltage-stabilized inverter of the first voltage regulator is connected to a first bit line of a semiconductor memory cell to be measured; and
a second voltage regulator, wherein the first and second voltage regulators are of identical structure, and wherein a first input of a voltage-stabilized inverter of the second voltage regulator is connected to a second bit line of a reference semiconductor memory cell, and wherein a difference between a current intensity of the first and second bit lines is indicative of the state of the semiconductor memory cell.
5. The sense amplifier according to claim 4, further comprising:
a differential element; and
an amplifying element, wherein a differential element output is connected with an amplifying element input;
wherein the differential element comprises:
a first current mirror for mirroring the first current from the first bit line to a first line; and
a second current mirror for mirroring the second current from the second bit line to a second line, wherein the first and second lines are connected with the amplifying element input via a node.
6. A semiconductor memory, comprising:
a bit line:
a memory cell coupled to the bit line;
a voltage regulator for the bit line, comprising:
a reference voltage source providing an output voltage at a substantially constant voltage;
a feedback transistor; and
a voltage-stabilized inverter comprising a first input connected to the bit line and to a source of the feedback transistor, a second input connected to the substantially constant voltage, an output connected to a gate of the feedback transistor to regulate a voltage on the bit line, an inverter transistor, a current source transistor parallel to the inverter transistor, and a current mirror between an operating voltage and the inverter transistor.
7. The memory according to claim 6,
wherein the inverter transistor comprises an inverter gate, an inverter source, and inverter drain, wherein the inverter gate is connected to the first input, the inverter drain is connected to the output, and the inverter source is at ground.
8. The memory according to claim 7, wherein the current source transistor and the inverter transistor are identical, so that the output voltage of the reference voltage source adjusts itself at the inverter gate of the inverter transistor.
9. The memory according to claim 6, wherein the voltage regulator is a first voltage regulator and the memory cell is a memory cell to be measured and the bit line is a first bit line, the memory further comprising:
a second voltage regulator, wherein the first and second voltage regulators are of identical structure, and wherein the second voltage regulator is connected to a second bit line of a reference memory cell, wherein a difference between a current intensity of the first and second bit lines is indicative of the state of the memory cell to be measured.
10. The memory according to claim 9, further comprising:
a differential element; and
an amplifying element, wherein a differential element output is connected with an amplifying element input;
wherein the differential element comprises:
a first current mirror for mirroring the first current from the first bit line to a first line; and
a second current mirror for mirroring the second current from the second bit line to a second line, wherein the first and second lines are connected with the amplifying element input via a node.
11. The memory according to claim 6, comprising:
wherein the memory cell is a non-volatile memory cell.
12. The memory according to claim 11, wherein the memory cell is a flash memory cell.
13. The memory according to claim 11, wherein the memory cell is an EEPROM memory cell.
14. A voltage regulator for a bit line of a semiconductor memory, comprising:
a reference voltage source providing a substantially constant voltage;
a feedback transistor; and
a voltage-stabilized inverting means including a first input connected to the bit line and to a source of the feedback transistor, a second input connected to the substantially constant voltage, an output connected to a gate of the feedback transistor which controls the feedback transistor to regulate a voltage on the bit line, an inverter transistor, a current source transistor parallel to the inverter transistor, and a current mirror between an operating voltage and the inverter transistor.
15. An integrated circuit comprising a voltage regulator comprising:
a reference voltage source providing a substantially constant reference voltage;
a feedback transistor;
a voltage-stabilized inverter comprising:
a first input connected to a bit line and to a source of the feedback transistor;
a second input connected to the substantially constant reference voltage;
an output connected to a control input of the feedback transistor to regulate a voltage on the bit line;
an inverter transistor
a current source transistor parallel to the inverter transistor; and
a current mirror between an operating voltage and the inverter transistor; and one or more memory components coupled to the bit line.
16. The integrated circuit according to claim 15,
wherein the inverter transistor comprises an inverter gate, an inverter source, and inverter drain, wherein the inverter gate is connected to the first input, the inverter drain is connected to the output, and the inverter source is at ground.