What is claimed is:
1. A protective covering comprising:
an electrostatically charged sheet having a top and bottom surface; and
an absorbent layer having top and bottom surfaces, said bottom surface of said absorbent layer being bonded to said top surface of said electrostatically charged sheet, said absorbent layer being divided into a plurality of cells for containing liquid spilled on said absorbent layer.
2. The protective covering of claim 1, wherein said absorbent layer comprises paper.
3. The protective covering of claim 1, wherein said absorbent layer comprises an open cell foam.
4. The protective covering of claim 3, wherein said foam is electrostatically charged.
5. The protective covering of claim 1, wherein said absorbent layer comprises a fibrous mat.
6. The protective covering of claim 5, wherein said fibrous mat is electrostatically charged.
7. The protective covering of claim 1, wherein said absorbent layer comprises a plurality of hydrophobic barriers, said hydrophobic barriers defining said cells.
8. The protective covering of claim 1 further comprising a hydrophobic layer bonded to said top surface of said absorbent layer, said hydrophobic layer having a plurality of pores therethrough, said pores allowing liquid spilled on said hydrophobic layer to penetrate said hydrophobic layer and be absorbed by said absorbent layer.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit package assembly, comprising:
a common die pad;
a first vertical n-channel metal oxide semiconductor field effect transistor (NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith;
a second vertical n-channel metal oxide semiconductor field effect transistor (NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith.
2. The circuit package assembly of claim 1 wherein the first NMOSFET is a high-side NMOSFET and wherein the second NMOSFET is a low-side NMOSFET
3. The circuit package assembly of claim 2 wherein the high-side NMOSFET comprises a bottom source n-channel lateral double diffused MOSFET (LDMOSFET) and wherein the low-side NMOSFET comprises a bottom drain n-channel vertical double diffused MOSFET (VDMOSFET).
4. The circuit package assembly of claim 2, wherein a gate pad and a drain pad of the high-side NMOSFET are located on a side of the high-side NMOSFET facing away from the common die pad, and wherein the gate pad and drain pad are electrically connected to gate and drain leads respectively.
5. The circuit package assembly of claim 1, wherein a gate pad and a source pad of the second NMOSFET are electrically connected to gate and source leads respectively through a plurality of bond wires.
6. The circuit package assembly of claim 2, wherein a drain pad of the high-side NMOSFET and a source pad of the low-side NMOSFET are located on a side of the high-side NMOSFET and the low-side NMOSFET respectively facing away from the common die pad, and wherein the drain pad and source pad are electrically connected to drain and source leads through first and second bond plates respectively.
7. The circuit package assembly of claim 6, wherein the first bond plate includes a first plurality of dimples formed thereon coupling the drain lead to a drain pad on the high-side NMOSFET, the dimples being positioned for contact with the drain pad and wherein the second bond plate includes a second plurality of dimples formed thereon coupling the source lead to a source pad on the low-side NMOSFET, the dimples being positioned for contact with the source pad.
8. The circuit package assembly of claim 7, wherein the first and second pluralities of dimples are soldered respectively to the drain pad and the source pad.
9. The circuit package assembly of claim 8, wherein a gate pad of the high-side NMOSFET and a gate pad of the low-side NMOSFET are electrically connected to gate leads through bond wires or wherein the gate pad of the high-side NMOSFET and the gate pad of the low-side NMOSFET are electrically connected to gate leads through high-side and low-side gate bond plates.
10. The circuit package assembly of claim 10, wherein the high-side gate bond plate includes a dimple formed thereon, the dimple being positioned for contact with the gate pad on the high-side NMOSFET andor wherein the low-side gate bond plate includes a dimple formed thereon coupling the gate lead to a gate pad on the low-side NMOSFET, the dimple being positioned for contact with the gate pad on the low-side NMOSFET.
11. The circuit package assembly of claim 10, wherein the dimple is soldered to the gate pad on the low-side NMOSFET.
12. The circuit package assembly of claim 2 wherein a drain pad of the high-side NMOSFET located on a side facing away from the common die pad and a source pad of the low-side NMOSFET located on a side facing away from the common die pad are electrically connected to drain and source leads respectively through one or more aluminum power ribbons.
13. The circuit package assembly of claim 12, wherein gate pads of the high-side NMOSFET and the low-side NMOSFET are electrically connected to gate leads through wires, or wherein gate pads of the high-side NMOSFET and the low-side NMOSFET are electrically connected to gate leads through bond plates or power ribbons.
14. The circuit package assembly of claim 2, wherein the high-side NMOSFET is a bottom drain NMOSFET having one or more drain pads on a bottom side and a gate pad and one or more source pads at a top side and is mounted to the common die pad in a \u201cflipped\u201d configuration as a \u201cflip chip\u201d with the top side proximate to and facing the common die pad, whereby the gate pad and the one or more source pads are proximate to and facing the common die pad.
15. The circuit package assembly of claim 14, wherein the drain pads of the high-side \u201cflipped\u201d NMOSFET and one or more source pads of the low-side NMOSFET are electrically connected to corresponding drain and source leads through corresponding high-side and low-side bond plates.
16. The circuit package assembly of claim 12, wherein the \u201cflip chip\u201d bond plate includes a plurality of dimples formed thereon adapted to couple the drain lead to the one or more drain pads on the high-side \u201cflipped\u201d NMOSFET, the dimples being positioned for contact with the drain pads.
17. The circuit package assembly of claim 16, wherein the high-side \u201cflipped\u201d NMOSFET further includes source and gate electrical connections formed using one or more solder balls.
18. The circuit package assembly of claim 17, wherein the low-side source bond plates include a bond plate having a plurality of dimples formed thereon, the bond plate being configured to couple the source lead to source pads on the low-side NMOSFET, the dimples being positioned for contact with the one or more source pads.
19. The circuit package assembly of claim 18, wherein the plurality of dimples on the low-side source bond plate are soldered to the one or more source pads on the low-side NMOSFET andor wherein a gate of the low-side NMOSFET is electrically connected to a gate lead through a low-side gate bond plate having a dimple formed thereon coupling the gate lead to a corresponding gate pad on the low-side NMOSFET, the dimples being positioned for contact with the gate pad.
20. The circuit package assembly of claim 19, wherein the dimple on the low-side gate bond plate is soldered to the gate pad.
21. The circuit package assembly of claim 14, wherein sources of the low-side NMOSFET are electrically connected to source leads through one or more conductive power ribbons or clips andor wherein a gate of the low-side NMOSFET is electrically connected to a gate lead through a conductive wire or clip.
22. The circuit package assembly of claim 21, wherein a drain of the high-side \u201cflipped\u201d NMOSFET is electrically connected to one or more drain leads through a conductive power ribbon or a conductive clip andor wherein a gate of the high-side \u201cflipped\u201d NMOSFET is electrically connected to a gate lead through a solder ball.
23. A circuit package assembly, comprising:
a common die pad;
a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith, wherein the high-side NMOSFET comprises a bottom source n-channel lateral double diffused MOSFET (LDMOSFET);
a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith, wherein the low-side NMOSFET is a vertical double diffused MOSFET (VDMOSFET).
24. A circuit package assembly, comprising:
a common die pad;
a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith, wherein the high-side NMOSFET is mounted to the common die pad in a \u201cflipped\u201d configuration as a \u201cflip chip\u201d;
a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith, wherein the low-side NMOSFET is a vertical double diffused MOSFET (VDMOSFET).
25. A circuit package assembly, comprising:
a common die pad;
a high-side n-channel metal oxide semiconductor field effect transistor (high-side NMOSFET) having an electrical contact to a source thereof on a side facing a surface of the common die pad and in electrical contact therewith;
a low-side standard n-channel metal oxide semiconductor field effect transistor (low-side NMOSFET) having an electrical contact to a drain thereof on a side facing the common die pad and in electrical contact therewith; and
a MOSFET driver integrated circuit (IC) having a high-side gate driver output coupled to a gate of the high-side NMOSFET and a low side gate driver coupled to a gate of the low-side NMOSFET.