1. A power supply device comprising:
a DC converter circuit including a rectifier circuit and first and second smoothing capacitors, which are connected in series and arranged between two power lines at an output side of the rectifier circuit, wherein the DC converter circuit rectifies and smooths input AC power and converts the input AC power into DC voltage;
an inverter circuit including a bridge circuit of first to fourth switching elements, wherein predetermined sets of the first to fourth switching elements are alternately activated and deactivated to convert the DC voltage to a predetermined AC voltage;
an auxiliary switching circuit including an auxiliary capacitor, which is connected between the two power lines between the DC converter circuit and the inverter circuit, fifth and sixth switching elements respectively arranged on the two power lines between the DC converter circuit and the auxiliary capacitor, seventh and eighth switching elements connected in series between the two power lines between the auxiliary capacitor and the first and sixth switching elements, and a switching unit that connects or disconnects a first node of the first and second smoothing capacitors and a second node of the seventh and eighth switching elements, wherein
the switching unit disconnects the first and second nodes when the input AC power has a first voltage value to supply a voltage across two terminals of the first and second smoothing capacitors to the inverter circuit, and
the switching unit connects the first and second nodes when the input AC power has a second voltage value that is two times greater than the first voltage value so that soft switching control is performed by activating and deactivating predetermined sets of the fifth to eighth switching elements, alternately supplying the inverter circuit with a voltage across the terminals of the first or second smoothing capacitor, and deactivating a predetermined one of the fifth to eighth switching elements before the first to fourth switching elements are deactivated to stop the voltage supplied to the inverter circuit;
a pulse width modulation control unit that adjusts an on pulse width of a control pulse signal provided to the first to fourth switching elements and adjusts an on pulse width of a control pulse signal provided to the fifth to eighth switching elements in accordance with the adjusted width;
a phase shift control unit that adjusts a phase difference of two control pulse signals provided to the same set of switching elements in the first to fourth switching elements or adjusts a phase difference of two control pulse signals provided to predetermined ones of the first to fourth switching elements and corresponding ones of the fifth to eighth switching elements; and
a control switching unit that operates the pulse width modulation control unit when a relatively large output is requested and operates the phase shift control unit when a relatively small output is requested,
wherein the control switching unit operates the phase shift control unit when an output is requested that may result in the on pulse width being smaller than the predetermined narrow pulse width to adjust a phase of the control pulse signal in a state in which the on pulse width of the control pulse signal provided to the first to fourth switching elements is fixed at a first narrow pulse width and the on pulse width of the control pulse signal provided to the fifth to eighth switching elements is fixed at a second narrow pulse width.
2. The power supply device according to claim 1, wherein the control switching unit operates the pulse width modulation control unit when an output is requested that sets the on pulse width to be larger than a predetermined narrow pulse width allowing for each of the switching elements to be sufficiently activated.
3. The power supply device according to claim 1, wherein the phase shift control unit adjusts the phase of the control pulse signal provided to the first to eighth switching elements so that the fifth to eighth switching elements are deactivated before the first to fourth switching elements are deactivated.
4. The power supply device according to claim 1, further comprising a switch control unit that controls the switching unit to connect the first and second nodes when the input AC power has the second voltage value and disconnects the first and second nodes when the input AC power has the first voltage value.
5. An arc machining power supply device comprising:
the power supply device according to claim 1; and
a rectifier circuit that rectifies the predetermined AC voltage provided from the power supply device and generates an arc machining voltage for performing arc machining on a machining subject.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device fabrication method comprising:
forming a second material film over a first material film formed over a work substrate, the first and second material films being different in material;
forming a first resist layer over the second material film;
performing a first exposure process on the first resist layer to form a first resist pattern of a uniform pattern density, the first resist pattern including a desired pattern and a dummy pattern;
forming a second material film pattern by doing anisotropic dry etching of the second material film using the first resist pattern as a mask;
removing the first resist pattern;
forming a second resist layer to cover the second material film pattern after the first resist pattern is removed;
performing a second exposure process on the second resist layer to form a second resist pattern, the second resist pattern covering a first part of the second material film pattern corresponding to the desired pattern;
removing a second part of the second material film pattern corresponding to the dummy pattern using the second resist pattern as a mask;
removing the second resist pattern; and
doing anisotropic dry etching of the first material film using the first part of the second material film pattern as a mask.
2. A semiconductor device fabrication method comprising:
forming a second material film over a first material film formed over a work substrate, the first and second material films being different in material;
forming a first resist layer over the second material film;
performing a first exposure process on the first resist layer to form a first resist pattern of a uniform pattern density, the first resist pattern including a desired pattern and a dummy pattern;
slimming the first resist pattern;
forming a second material film pattern by doing anisotropic dry etching of the second material film using the slimmed first resist pattern as a mask;
removing the slimmed first resist pattern;
forming a second resist layer to cover the second material film pattern after the slimmed first resist pattern is removed;
performing a second exposure process on the second resist layer to form a second resist pattern, the second resist pattern covering a first part of the second material film pattern corresponding to the desired pattern;
removing a second part of the second material film pattern corresponding to the dummy pattern using the second resist pattern as a mask;
removing the second resist pattern; and
doing anisotropic dry etching of the first material film using the first part of the second material film pattern as a mask.
3. A semiconductor device fabrication method comprising:
forming a second material film over a first material film formed over a work substrate, the first and second material films being different in material;
forming a first resist layer over the second material film;
performing a first exposure process on the first resist layer to form a first resist pattern of a uniform pattern density, the first resist pattern including a desired pattern and a dummy pattern;
forming a second material film pattern by doing anisotropic dry etching of the second material film using the first resist pattern as a mask;
removing the first resist pattern;
slimming the second material film pattern;
forming a second resist layer to cover the slimmed second material film pattern;
performing a second exposure process on the second resist layer to form a second resist pattern, the second resist pattern covering a first part of the slimmed second material film pattern corresponding to the desired pattern;
removing a second part of the slimmed second material film pattern corresponding to the dummy pattern using the second resist pattern as a mask;
removing the second resist pattern; and
doing anisotropic dry etching of the first material film using the first part of the slimmed second material film pattern as a mask.
4. A semiconductor device fabrication method comprising:
forming a second material film over a first material film formed over a work substrate, the first and second material films being different in material;
forming a first resist layer over the second material film;
performing a first exposure process on the first resist layer to form a first resist pattern of a uniform pattern density, the first resist pattern including a desired pattern and a dummy pattern;
slimming the first resist pattern;
forming a second material film pattern by doing anisotropic dry etching of the second material film using the slimmed first resist pattern as a mask;
removing the slimmed first resist pattern;
slimming the second material film pattern;
forming a second resist layer to cover the slimmed second material film pattern;
performing a second exposure process on the second resist layer to form a second resist pattern, the second resist pattern covering a first part of the slimmed second material film pattern corresponding to the desired pattern;
removing a second part of the slimmed second material film pattern corresponding to the dummy pattern using the second resist pattern as a mask;
removing the second resist pattern; and
doing anisotropic dry etching of the first material film using the first part of the slimmed second material film pattern remained in the part corresponding to the desired pattern as a mask.
5. The semiconductor device fabrication method according to claim 1, wherein the second material film is made up of at least one of a hard mask material film, an anti-reflection material film, and a planarization material film.
6. The semiconductor device fabrication method according to claim 1, wherein the second material film is made up of at least one of a silicon oxidation (SiO2) film, a silicon nitride (Si3N4) film, a silicon oxynitride (SiON) film, an aluminum oxide (Al2O3) film, a silicon carbide (SiC) film, and a carbon (C) film.
7. The semiconductor device fabrication method according to claim 1, wherein a gate layer pattern for transistors is formed by the process of doing anisotropic dry etching of the first material film.