What is claimed is:
1. A visual axis detecting apparatus comprising:
a visual axis detection circuit for detecting a visual axis of an observer;
an arithmetic circuit for performing an arithmetic operation of calculating a distributed state of variations of visual axis positions obtained in a plurality of visual axis detections executed by the visual axis detection circuit in a state in which the observer is observing a predetermined point, with respect to said predetermined point;
a determination circuit for determining a condition of the visual axis according to the result of detection by the visual axis detection circuit; and
a change circuit for changing a determination process of determining the condition of the visual axis by the determination circuit, according to the distributed state of variations.
2. The apparatus according to claim 1, further comprising:
a storage circuit for storing the distributed state calculated by said arithmetic circuit, wherein said change circuit changes the number of detections by said visual axis detection circuit to a smaller number when the distributed state of variations is small, but the change circuit changes the number of detections by said visual axis detection circuit to a larger number when the distributed state of variations is large, and wherein said determination circuit determines the condition of the visual axis on the basis of the number of detections changed by the change circuit.
3. The apparatus according to claim 2, wherein said determination circuit determines that a position of the visual axis is an average position of a plurality of visual axis positions detected by said visual axis detection circuit.
4. The apparatus according to claim 1, wherein said arithmetic circuit calculates a standard deviation of a plurality of visual axis positions.
5. The apparatus according to claim 1, wherein said predetermined point is displayed on a screen.
6. The apparatus according to claim 5, wherein a plurality of zones are displayed on said screen and a zone is selected out of said plurality of zones according to the condition of the visual axis determined by said determination circuit.
7. The apparatus according to claim 6, wherein said screen is a focusing screen of a camera.
8. The apparatus according to claim 1, further comprising:
a mode setting member for setting a mode of performing the arithmetic operation by said arithmetic circuit and a mode of performing the determination by said determination circuit.
9. A visual axis detecting apparatus comprising:
a screen in which a plurality of zones are formed;
a visual axis detection circuit for detecting a visual axis of an observer;
an arithmetic circuit for performing an arithmetic operation of calculating a distributed state of variations of visual axis positions obtained in a plurality of visual axis detections executed by the visual axis detection circuit in a state in which the observer is observing a predetermined point on said screen, with respect to said predetermined point;
a selection circuit for selecting one of said plurality of zones according to the result of detection by said visual axis detection circuit; and
a change circuit for changing a selection process by said selection circuit according to the distributed state of variations.
10. The apparatus according to claim 9, further comprising:
a storage circuit for storing the distributed state calculated by said arithmetic circuit, wherein said change circuit changes the number of detections by said visual axis detection circuit to a smaller number when the distributed state of variations is small, but the change circuit changes the number of detections by said visual axis detection circuit to a larger number when the distributed state of variations is large, and wherein said selection circuit selects one of said plurality of zones on the basis of the number of detections changed by the change circuit.
11. The apparatus according to claim 10, wherein said selection circuit selects a zone located at an average position of a plurality of visual axis positions detected by said visual axis detection circuit.
12. The apparatus according to claim 9, wherein said arithmetic circuit calculates a standard deviation of a plurality of visual axis positions.
13. The apparatus according to claim 9, wherein said screen is a focusing screen of a camera.
14. The apparatus according to claim 9, further comprising:
a mode setting member for setting a mode of Performing the arithmetic operation by said arithmetic circuit and a mode of performing the selection by said selection circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a semiconductor structure, the method comprising:
providing a semiconductor substrate; and
forming a memory cell at a surface of the semiconductor substrate comprising:
forming a gate dielectric on the semiconductor substrate;
forming a control gate on the gate dielectric;
forming a first and a second tunneling layer on a source side and a drain side of memory cell, respectively, wherein the first and the second tunneling layers each comprise a vertical portion on sidewalls of the gate dielectric and the control gate, and a horizontal portion on a top surface of the semiconductor substrate;
tilt implanting a lightly doped source region underlying the first tunneling layer, wherein the tilt implanting tilts only from the source side to the drain side, and wherein a portion of the semiconductor substrate under the second tunneling layer is free from the tilt implanting;
forming a storage on the horizontal portion of the second tunneling layer;
forming a source region in the semiconductor substrate and adjacent to the first tunneling layer; and
forming a drain region in the semiconductor substrate and adjacent to the second tunneling layer;
wherein the completed formed drain region is spaced apart from a respective edge of the control gate and at least a portion of the second tunneling layer overlies a portion of the semiconductor substrate free from impurities from the tilt implanting and the forming of the drain region.
2. The method of claim 1, wherein the step of tilt implanting is performed after the step of forming the storage.
3. The method of claim 1, wherein the storage comprises silicon nitride.
4. The method of claim 1, wherein the lightly doped source region comprises a portion underlying the control gate.
5. The method of claim 1, wherein the lightly doped source region is spaced apart from a respective edge of the control gate.
6. The method of claim 1, wherein the storage is L-shaped, and wherein the memory cell further comprises a dielectric material on a horizontal portion of the storage, and wherein the dielectric material does not extend over the drain region.
7. A method of forming a semiconductor structure, the method comprising:
providing a semiconductor substrate;
forming a gate stack comprising:
forming a gate dielectric on the semiconductor substrate; and
forming a control gate on the gate dielectric;
forming a dielectric layer on the gate stack and the semiconductor substrate;
patterning the dielectric layer to form two tunneling layers on opposite sides of the gate stack, wherein the tunneling layers each comprise a vertical portion on a sidewall of the gate stack and a horizontal portion on a top surface of the semiconductor substrate;
tilt implanting an impurity into the semiconductor substrate to form a lightly doped source region and a lightly doped drain region, wherein the tilt implanting only tilts from a source side to a drain side;
forming a storage layer after the step of forming the dielectric layer;
patterning the storage layer to form storages, wherein each of the storages is on a horizontal portion of one of the tunneling layers; and
implanting a source region and a drain region using the storages as masks;
wherein the completed formed drain region including the lightly doped drain region is spaced apart from a respective edge of the control gate and at least a portion of the second tunneling layer overlies a portion of the semiconductor substrate free from impurities implanted during the tilt implanting and the implanting of the drain region.
8. The method of claim 7, wherein the lightly doped drain region is spaced apart from a respective edge of the control gate by between about 100 \u212b and about 200 \u212b.
9. The method of claim 7, wherein the step of tilt implanting is performed before the step of forming the dielectric layer.
10. The method of claim 7, wherein the step of tilt implanting is performed after the step of forming the dielectric layer and before the step of forming the storage layer.
11. The method of claim 7, wherein the step of implanting is performed after the step of patterning the storage layer.
12. The method of claim 7, wherein the step of implanting the source and the drain regions is performed before the step of patterning the dielectric layer.
13. The method of claim 7, wherein the dielectric layer has a thickness of between about 30 \u212b and about 100 \u212b.
14. The method of claim 7, wherein the storages comprise silicon nitride.
15. The method of claim 7, wherein the lightly doped drain region comprises a portion not overlapped by the drain region.
16. he method of claim 7, wherein the lightly doped drain region is overlapped by the drain region.
17. A method of forming a memory cell, the method comprising:
providing a semiconductor substrate;
forming a gate stack comprising:
forming a gate dielectric on the semiconductor substrate; and
forming a control gate on the gate dielectric;
forming tunneling layers on opposite side of the gate stack, wherein each of the tunneling layer comprises a vertical portion on a sidewall of the gate stack, and a horizontal portion on a top surface of the semiconductor substrate;
forming storages, wherein each of the storages is on a horizontal portion of one of the tunneling layers;
tilt implanting an impurity into the semiconductor substrate after the step of forming the storages to form a lightly doped source region and a lightly doped drain region, wherein the tilt implanting only tilts from a source side to a drain side, and wherein the lightly doped source region and the lightly doped drain region are both spaced apart from respective edges of the control gate; and
implanting a source region and a drain region using the storages as masks.
18. The method of claim 17, wherein the lightly doped source region and a respective edge of the control gate have a first distance, and wherein the lightly doped drain region and a respective edge of the control gate have a second distance, and wherein the first distance is less than the second distance by greater than about 100 \u212b.
19. The method of claim 17, wherein the lightly doped drain region is overlapped by the drain region.