1. A multi-stage output buffer having a differential input and a differential output, comprising:
an emitter follower circuit coupled to the differential input, and configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof;
an emitter coupled pair circuit coupled to the output of the emitter follower circuit, wherein the emitter coupled pair circuit is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof;
a differential base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer, wherein the base-grounded configuration transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed and signal amplitude of the buffer;
a bias current circuit coupled to the base-grounded configuration transistor circuit, and configured to provide a DC bias current to keep transistors in the base-grounded configuration transistor circuit from turning off when transistors in the emitter coupled pair circuit turn off, thereby further improving a speed, linearity and signal amplitude of the output buffer; and
a first bias voltage generation circuit coupled to the emitter follower circuit, and configured to establish a first DC bias voltage at the input of the emitter follower circuit about which a differential signal varies.
2. The multi-stage output buffer of claim 1, further comprising a capacitive coupling at an input of the emitter follower circuit, wherein a capacitive coupling provides a DC isolation between the input circuit and the emitter follower circuit when the input circuit is coupled thereto.
3. The multi-stage output buffer of claim 1, wherein the first DC bias voltage comprises a voltage level that prevents one or more transistors associated with the emitter follower circuit from saturating or quasi-saturating, thereby facilitating a high speed operation of the emitter follower circuit.
4. The multi-stage output buffer of claim 1, wherein the emitter follower circuit comprises:
a first bipolar transistor having a base terminal coupled to a first portion of the differential input; and
a second bipolar transistor having a base terminal coupled to a second portion of the differential input,
wherein a voltage at emitter terminals of the first and second bipolar transistors substantially follows a voltage at the base terminals thereof, wherein the voltage at the base terminals is associated with a differential signal provided at the differential input of the multi-stage output buffer.
5. The multi-stage output buffer of claim 4, wherein the emitter coupled pair circuit comprises:
a third bipolar transistor having a base terminal coupled to an emitter terminal of the first bipolar transistor, and having an emitter terminal; and
a fourth bipolar transistor having a base terminal coupled to an emitter terminal of the second bipolar transistor, and having an emitter terminal coupled to the emitter terminal of the third bipolar transistor emitter terminal,
wherein a collector terminal of the third and fourth bipolar transistors form a differential output thereof.
6. The multi-stage output buffer of claim 5, wherein the base-grounded configuration transistor circuit comprises fifth and sixth bipolar transistors, wherein the fifth bipolar transistor has a base terminal coupled to a base terminal of the sixth bipolar transistor to thereby form an AC or virtual ground node thereat, and wherein an emitter terminal of the fifth and sixth bipolar transistors are coupled to respective output portions of the emitter coupled pair circuit, and wherein collector terminals of the fifth and sixth bipolar transistors form the differential output of the multi-stage output buffer.
7. The multi-stage output buffer of claim 1, wherein the base-grounded configuration transistor circuit comprises first and second bipolar transistors, wherein the first bipolar transistor has a base terminal coupled to a base terminal of the second bipolar transistor to thereby form an AC or virtual ground node thereat, and wherein an emitter terminal of the first and second bipolar transistors are coupled to respective output portions of the emitter coupled pair circuit, and wherein collector terminals of the first and second bipolar transistors form the differential output of the multi-stage output buffer.
8. The multi-stage output buffer of claim 1, wherein the bias current circuit is coupled to an input of the base-grounded configuration transistor circuit.
9. A multi-stage output buffer having a differential input and a differential output, comprising:
an emitter follower circuit coupled to the differential input, and configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof;
an emitter coupled pair circuit coupled to the output of the emitter follower circuit, wherein the emitter coupled pair circuit is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof;
a differential base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer, wherein the base-grounded configuration transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed and signal amplitude of the buffer; and
a bias current circuit coupled to the base-grounded configuration transistor circuit, and configured to provide a DC bias current to keep transistors in the base-grounded configuration transistor circuit from turning off when transistors in the emitter coupled pair circuit turn off, thereby further improving a speed, linearity and signal amplitude of the output buffer, wherein the bias current circuit comprises:
a pair of series-coupled resistors connected across a differential input of the base-grounded configuration transistor circuit forming an AC or virtual ground node at a node between the series-coupled resistors; and
a current source coupled between the AC or virtual ground node and a predetermined potential.
10. The multi-stage output buffer of claim 9, wherein the current source comprises a resistor.
11. The multi-stage output buffer of claim 1, wherein the multi-stage output buffer further comprises an inductance coupled between the emitter coupled pair circuit and the base-grounded configuration transistor circuit, and operable to facilitate an impedance matching therebetween.
12. The multi-stage output buffer of claim 11, wherein the inductance comprises a micro-strip transmission line.
13. A multi-stage output buffer having a differential input and a differential output, comprising:
an emitter follower circuit coupled to the differential input, and configured to provide a substantially high input impedance at an input thereof, and provide a substantially low output impedance at an output thereof;
an emitter coupled pair circuit coupled to the output of the emitter follower circuit, wherein the emitter coupled pair circuit is configured to amplify the signal and further isolate an input circuit when coupled to the differential input of the multi-stage output buffer from an external load when coupled to the differential output thereof;
a differential base-grounded configuration transistor circuit coupled to an output of the emitter coupled pair circuit and having an output coupled to the differential output of the multi-stage output buffer, wherein the base-grounded configuration transistor circuit is configured to reduce a load impedance at the output of the emitter coupled pair circuit, thereby improving a speed and signal amplitude of the buffer;
a bias current circuit coupled to the base-grounded configuration transistor circuit, and configured to provide a DC bias current to keep transistors in the base-grounded configuration transistor circuit from turning off when transistors in the emitter coupled pair circuit turn off, thereby further improving a speed, linearity and signal amplitude of the output buffer; and
an inductive voltage divider circuit coupled between an input of the emitter follower circuit and the differential input of the multi-stage output buffer, and configured to weaken a loading of the input circuit when coupled thereto.
14. The multi-stage output buffer of claim 13, wherein the inductive voltage divider comprises a first and second pair of series-connected inductances coupled to the differential input of the multi-stage output buffer, wherein an output of the inductive voltage divider comprises a pair of nodes between the first and second series-connected inductances, respectively, and wherein such nodes are coupled to the input of the emitter follower circuit.
15. The multi-stage output buffer of claim 14, wherein the first and second pair of series-connected inductances each comprise:
a first differential micro-strip line having a first terminal configured to be coupled to one differential output of the input circuit; and
a second differential micro-strip line having a first terminal coupled to a second terminal of the first differential micro-strip line forming one of the pair of nodes, and a second terminal coupled to a predetermined potential.
16. The multi-stage output buffer of claim 15, wherein each micro-strip line comprises a pair of substantially parallel, longitudinally extending conductors having a plurality of shorting conductors extending thereacross at differing positions along a length of the conductor pair, wherein a continuity of one or more of the shorting conductors influences a magnitude of an inductance associated therewith.
17. The multi-stage output buffer of claim 14, wherein a relative magnitude of the first and second series-connected inductances in each pair influence a balance between an amount of loading at an output of an input circuit when coupled thereto and an amplitude of a differential signal of the input circuit provided to the differential input of the multi-stage output buffer.
18. The multi-stage output buffer of claim 17, wherein the first and second pair of series connected inductances each comprise:
a first differential micro-strip line having a first terminal configured to be coupled to one differential output of the input circuit; and
a second differential micro-strip line having a first terminal coupled to a second terminal of the first differential micro-strip line forming one of the pair of nodes, and a second terminal coupled to a predetermined potential.
19. The multi-stage output buffer of claim 18, wherein each micro-strip line comprises a pair of substantially parallel, longitudinally extending conductors having a plurality of shorting conductors extending thereacross at differing positions along a length of the conductor pair, wherein a continuity of one or more of the shorting conductors influences a magnitude of an inductance associated therewith.
20. The multi-stage output buffer of claim 1, further comprising an impedance matching circuit coupled between the base-grounded configuration transistor circuit and the differential output of the multi-stage output buffer, and configured to be coupled to an external load, the impedance matching circuit comprising one or more inductances per output node thereof, wherein the one or more inductances of the matching circuit comprises one or more micro-strip transmission lines.
21. The multi-stage output buffer of claim 20, wherein the micro-strip transmission lines comprise a pair of substantially parallel, longitudinally extending conductors having a plurality of shorting conductors extending thereacross at differing positions along a length of the conductor pair, wherein a continuity of one or more of the shorting conductors influences a magnitude of an inductance of the micro-strip transmission lines.
22. A multi-stage output buffer having a differential input and a differential output, comprising:
an impedance transformation means coupled to an inductive voltage dividing means, and operable to provide a large input impedance at an input thereof and a low output impedance at an output thereof to substantially decouple any succeeding stages from an input circuit at the differential input when coupled thereto;
a further decoupling and signal amplification means coupled to the impedance transformation means, and operable to further decouple the external load from the input circuit when coupled thereto, and to increase an output signal amplitude;
a load impedance reducing means coupled to the further decoupling and signal amplification means, and operable to reduce a load impedance at an output of the further decoupling and signal amplification means to improve a speed and signal amplitude of the output buffer means; and
a bias current means coupled to the load impedance reducing means, and operable to provide a current to prevent active elements associated with the load impedance reducing means from turning off when active elements associated with the further decoupling and signal amplification means turn off, thereby improving a speed, linearity and output signal amplitude of the multi-stage output buffer.
23. The multi-stage output buffer of claim 22, further comprising a loading manipulation means coupled between the differential input of the multi-stage output buffer and the impedance transformation means, and operable to reduce a loading associated with an input circuit when coupled to the differential input of the multi-stage output buffer circuit.
24. The multi-stage output buffer of claim 23, wherein the loading manipulation means comprises an inductive voltage dividing means configured to provide a differential signal that is related to a differential output signal of the input circuit when coupled thereto.
25. The multi-stage output buffer of claim 22, wherein the impedance transformation means comprises an emitter follower pair circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A color filter substrate for a liquid crystal panel, the liquid crystal panel comprising:
an array substrate, wherein a plurality of first pixel electrodes and a plurality of first common electrodes are alternatively disposed on a side of the array substrate facing the color filter substrate; and
a plurality of sets of electrode structures formed on a side of the color filter substrate, each set of electrode structure being separate from one another and comprising a second pixel electrode and a second common electrode for generating a horizontal electric field between the second pixel electrode and the second common electrode by applying a voltage, in any two neighboring sets of electrode structure, the second pixel electrode and the second common electrode are disposed in opposite order, and each of the electrodes in one of the two neighboring sets of electrode structure not being shared with another set of electrode structure;
wherein a distance between the second pixel electrode and the neighboring second common electrode of the electrode structure is smaller than a distance between the first pixel electrode and the neighboring first common electrode.
2. The color filter substrate of claim 1, wherein: in any two neighboring sets of electrode structure, the distance between the second pixel electrode and the second common electrode is the same.
3. The color filter substrate of claim 2, wherein: each of the second pixel electrode and the second common electrode has a width of 2\u02dc3 \u03bcm; the distance between the second pixel electrode and the neighboring second common electrode is 2\u02dc5 \u03bcm.
4. The color filter substrate of claim 1, wherein: each of the second pixel electrode and the second common electrode has a width of 2\u02dc3 \u03bcm; the distance between the second pixel electrode and the neighboring second common electrode is 2\u02dc5 \u03bcm.
5. A liquid crystal panel comprising an array substrate, a color filter substrate, and a liquid crystal layer formed between the array substrate and the color filter substrate, wherein:
a plurality of first pixel electrodes and a plurality of first common electrodes are alternatively disposed on a side of the array substrate facing the color filter substrate;
a plurality of sets of electrode structures are formed on a side of the color filter substrate facing the array substrate, each set of electrode structure being separate from one another and comprising a second pixel electrode and a second common electrode, the second pixel electrode and the second common electrode in each set of electrode structure are symmetrically distributed on both sides of an orthographic projection of the first pixel electrode or the first common electrode on the color filter substrate, and wherein in any two neighboring sets of electrode structure, the pixel electrode and the common electrode are disposed in opposite order, and each of the electrodes in one of the two neighboring sets of electrode structure not being shared with another set of electrode structure;
wherein a distance between the second pixel electrode and the neighboring second common electrode of the electrode structure is smaller than a distance between the first pixel electrode and the neighboring first common electrode.
6. The liquid crystal panel of claim 5, wherein: each of the first pixel electrode, the second pixel electrode, the first common electrode and the second common electrode has a width of 2\u02dc3 \u03bcm; the distance between the second pixel electrode and the neighboring second common electrode of the electrode structure is 2\u02dc5 \u03bcm; the distance between the first pixel electrode and the neighboring first common electrode is 5\u02dc10 \u03bcm.
7. A liquid crystal display device comprising the liquid crystal panel of claim 5.