1. A device for recovering electric energy in an AC motor-driven electric vehicle, the device comprising:
a) a battery;
b) a single-phase or three-phase inverter;
c) a single-phase or three-phase inductor, the single-phase or three-phase inductor comprising a primary coil and a secondary coil;
d) an AC motor;
e) a rectifier bridge or a second inverter; and
f) a charger;
wherein
an anode and a cathode of the battery are connected to input ends of the single-phase or three-phase inverter, respectively; an output end of the single-phase or three-phase inverter is connected to the AC motor via the primary coil of the single-phase or three-phase inductor;
an output end of the secondary coil of the single-phase or three-phase inductor is connected to an input end of the rectifier bridge or the second inverter; output ends of the rectifier bridge are connected to the anode and the cathode of the battery, respectively;
the inductor is employed to rectify the current and regulate the voltage; the primary coil of the single-phase or three-phase inductor is in series connection with the load of the AC motor; when the AC motor works, the current and the voltage on the primary coil of the single-phase or three-phase inductor produce an electromagnetic induction and influence the secondary coil of the single-phase or three-phase inductor to produce the AC current and voltage on the secondary coil; the AC current and voltage is further rectified and inverted into a direct current by the rectifier bridge or the second inverter, and the direct current is input to the battery for electric energy recovery; and
the charger is connected to the anode and the cathode of the battery for supplying power from an external power supply.
2. The device of claim 1, wherein
the single-phase or three-phase inductor comprises: a magnetic core, a coil, a mounting bracket, a skeleton, and an insulating material; and
the single-phase or three-phase inductor is assembled by winding the coil on the skeleton, inserting the magnetic core inside the coil, fixing the coil on the mounting bracket, and using the insulating material for package.
3. The device of claim 2, wherein the coil is made of an enamel-covered wire or an insulating conductive material.
4. The device of claim 1, wherein the AC motor is provided with a speed controller for controlling a rotary speed of the AC motor.
5. The device of claim 1, wherein the battery is a battery pack or a single battery.
6. The device of claim 1, wherein the battery comprises a power manager for management of charging and discharging of the battery.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A device, comprising:
a silicon substrate;
a semiconducting fin extending outward from a top surface of the silicon substrate to a fin height, the fin including a channel of the device;
a source extending above the silicon substrate to a source height and in a transverse orientation with respect to the fin, the source abutting a first end of the fin, the source doped so as to supply charge to the channel;
a drain extending above the silicon substrate to a drain height and in a transverse orientation with respect to the fin, the drain abutting a second end of the fin, the drain doped so as to drain charge from the channel; and
a gate structure wrapping around at least three sides of the fin, the gate structure configured to control current in the channel in response to an applied voltage.
2. The device of claim 1 wherein the fin height, the source height, and the drain height are substantially equal.
3. The device of claim 1 wherein the fin, source, and drain are portions of a single contiguous layer on top of the silicon substrate.
4. The device of claim 1 wherein the fin, source, and drain are portions of a top layer of the silicon substrate.
5. The device of claim 1 wherein the gate structure is a dual gate having two independent nodes separated by an insulator, each of the independent nodes being capacitively coupled to the channel.
6. The device of claim 1, further comprising additional semiconducting fins extending between the source and drain, each of the additional fins including a channel, the gate structure wrapping around at least three sides of each additional fin and providing a single electrical node that controls current flow in the channels in response to the applied voltage.
7. The device of claim 6 wherein the fins are coupled to a common source and a common drain.
8. The device of claim 1 wherein the gate structure includes at least one gate electrode and a gate oxide disposed between the gate electrode and the channel.
9. The device of claim 1 wherein the substrate includes one or more of a buried oxide layer, a strained silicon layer, and a strained heterostructure layer.
10. The device of claim 1 wherein the silicon substrate includes components that impart strain to at least one channel.
11. The device of claim 1 wherein the silicon substrate is a fully-depleted silicon-on-insulator substrate.
12. An integrated circuit including a plurality of devices as claimed in claim 6, wherein no trench isolation structures exist in the substrate between adjacent ones of the plurality of devices.
13. The integrated circuit of claim 12, further comprising metal interconnects coupling a plurality of the devices, the metal interconnects made of a same material as the gate electrode.
14. The integrated circuit of claim 13 wherein the metal interconnects coupling a plurality of the devices include doped contacts.
15. A static read-only memory cell, comprising:
pairs of n-type FinFETs in which respective fins, source regions, and drain regions are portions of a same layer on top of a silicon substrate; and
pairs of p-type FinFETs in which respective fins, source regions, and drain regions are portions of the same layer,
the pairs of n-type FinFETs and the pairs of p-type FinFETs arranged to form cross-coupled inverters.
16. The memory cell of claim 15 wherein each pair of FinFETs is configured as a dual gate device in which current flow in a single channel is controlled by two independent nodes.
17. A memory cell array that includes static read-only-memory cells according to claim 15, the memory cells arranged in rows and columns, and the memory cells being electrically accessible via control lines coupling the rows and columns.
18. The memory cell array of claim 17 wherein the memory cells further comprise local interconnects having doped contacts, wherein portions of the control lines include portions of the local interconnects.
19. The memory cell of claim 15 wherein the single layer of silicon is a strained silicon layer.
20. The memory cell of claim 19 in which the strained silicon layer includes SiGe.