1. A memory device comprising:
an array of memory cells positioned in a first block and a second block, the memory cells being arranged in rows and columns;
a plurality of bit lines coupled to the memory cells;
a plurality of word lines coupled to the memory cells;
a sense amplifier positioned between the first block and the second block;
a plurality of electrical connections between said sense amplifier and said bit lines; and
a plurality of isolation transistors in series with said electrical connections, said isolation transistor being located within the first and second blocks and being spaced from said sense amplifier.
2. The memory device of claim 1 wherein said isolation transistors have source and drain regions having the same dimensions as source and drain regions of said memory cells.
3. The memory device of claim 1 wherein said sense amplifier has transistors with source and drain regions having a first size and said memory cells have transistors with source and drain regions having a second size, the second size being smaller than the first size.
4. The memory device of claim 1 wherein said isolation transistor has a source region electrically connected to said bit lines, a drain region electrically connected to an input of said sense amplifier, and a gate region electrically connected to an isolation control signal line, such that said isolation transistor provides a series electrical connection between said bit lines and said sense amplifier.
5. The memory device of claim 4 wherein the isolation control signal has a voltage level greater than a voltage level on said bit lines such that substantially all the voltage on said bit lines is present at the input of said sense amplifier.
6. An integrated circuit structure in a memory device comprising:
a substrate of semiconductor material of a first conductivity type;
an array of memory cells on said substrate, said memory cells being arranged in rows and columns, said memory cells being positioned into blocks;
a plurality of bit line pairs coupled to the memory cells;
a plurality of sense amplifiers in said substrate, said sense amplifiers being positioned between blocks of memory cells; and
a plurality of first isolation transistors being electrically connected in series between said sense amplifiers and said bit lines, said isolation transistors being positioned within the blocks of memory cells and spaced from said sense amplifiers.
7. The integrated circuit of claim 6, further comprising:
a plurality of word lines coupled to gates of the memory cells and gates of said first isolation transistors, said word lines being coupled to a source of a boosted gate voltage.
8. The integrated circuit of claim 6 wherein said sense amplifiers have transistors having a first dimension and said memory cells have transistors having a second dimension, the second dimension being less than the first dimension.
9. The integrated circuit of claim 6 wherein the first isolation transistors are n-channel transistors.
10. The integrated circuit of claim 6, further comprising:
a plurality of second isolation transistors that are p-channel transistors positioned between said sense amplifiers and spaced from the blocks of memory cells, said second isolation transistors and said first isolation transistors being electrically connected such that said first and second isolation transistors form full transmission gates in series with the sense amplifiers.
11. A method for minimizing dynamic RAM layout, the method comprising the steps of:
providing a substrate of semiconductor material of a first conductivity type;
forming an array of memory cells on the substrate, the memory cells being arranged in rows and columns, the memory cells being positioned into blocks;
forming a plurality of bit line pairs coupled to the memory cells;
forming a plurality of sense amplifiers in the substrate, the sense amplifiers being positioned between adjacent blocks of memory cells; and
forming a plurality of first isolation transistors in the substrate, the first isolation transistors having a second conductivity type and being connected in series between the sense amplifiers and the bit lines, the first isolation transistors being positioned within the blocks of memory cells and spaced from the sense amplifiers.
12. The method of claim 11, further comprising:
forming a plurality of word lines coupled to gates of the memory cells and gates of the first isolation transistors, the word lines being coupled to a source of a boosted gate voltage.
13. The method of claim 11, further comprising the step of:
forming a plurality of second isolation transistors in the substrate, the second isolation transistors having a first conductivity type and being positioned within the sense amplifiers, the second isolation transistors being spaced from the blocks of memory cells, the second isolation transistors and the first isolation transistors being electrically connected such that the first and second isolation transistors form full transmission gates.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of manufacturing, storing and transporting hydrogen and oxygen gas, comprising:
feeding water under hydrostatic pressure from a body of water by gravity down through a pipe to the interior bottom of a deep sealed production chamber, which is rigid and noncollapsible;
producing hydrogen and oxygen gas in and under the applied pressure of said water at the bottom of said production chamber with electrolysis,
capturing the produced oxygen gas in an oxygen escape pipe extending from the bottom of said production chamber to exterior of said production chamber, said oxygen gas escape pipe containing a positive anode electrode for the electrolysis in a bottom end of said oxygen pipe,
storing the produced hydrogen gas under pressure above said water under hydrostatic pressure in said sealed production chamber by directly contacting said hydrogen gas thereunder with said water under hydrostatic pressure from said body of water;
periodicallly releasing said stored hydrogen gas in said production chamber for transportation under said hydrostatic pressure while sustaining a pressurized state of the hydrogen gas during expulsion of stored gas volume from said production chamber by continuously applying the hydrostatic pressure of replenished water from said body of water to the stored hydrogen gas volume, thereby enabling such gas to be transported or restored in a pressurized state without the need for further energy consumption to compress the hydrogen gas.
2. The method of claim 1, including also capturing and storing said produced oxygen gas under pressure in a sealed container by directly contacting said oxygen gas thereunder with said water under hydrostatic pressure from said body of water.
3. The method of claim 1, including providing a floating seal on said water in said production chamber for thereby segregating said stored hydrogen gas from said water thereunder.
4. The method of claim 1, providing said production chamber from an underground pit.
5. The method of claim 1 wherein said water is fed into said production chamber from the bottom portion of a body of water.
6. The method of claim 1, wherein said electrolysis is energized by electricity generated from solar panels or wind mill generators.
7. The method of claim 6, wherein said produced hydrogen and oxygen are burned at selected times for generating electricity.
8. The method of claim 1, wherein said high pressure of said production chamber is in excess of 500 psi.
9. The method of claim 1, wherein th depth of said production chamber is in excess of 100 feet.