We claim:
1. An integrated circuit, comprising:
a terminal for supplying a digital signal;
a controllable driver circuit having a driver input connected to said terminal for receiving the digital signal and a driver output for outputting the digital signal;
an actuating circuit for actuating the driver circuit as a function of a clock signal, said actuating circuit having an actuating input for receiving the clock signal; and
a comparator device having:
a first comparator input for receiving the clock signal;
a second comparator input connected to said driver output for receiving the digital signal; and
a comparator output,
said comparator device outputting, from said comparator output, an output signal having:
a first state if a signal transition of the clock signal at said first comparator input takes place before a signal transition of the digital signal at said second comparator input; and
a second state if the signal transition of the clock signal at said first comparator input takes place after the signal transition of said digital signal at said second comparator input.
2. The integrated circuit according to claim 1, wherein said comparator device stores the first and second states of said output signal.
3. The integrated circuit according to claim 1, including a flipflop circuit having a first setting input, a second setting input, and a flipflop output;
said first comparator input connected to said first setting input;
said second comparator input connected to said second setting input;
said comparator output connected to said flipflop output; and
said comparator device programmed to produce the output signal indicating which of said first comparator input and said second comparator input receives a signal transition first.
4. The integrated circuit according to claim 1, including a function unit connected to said comparator output and to said actuation circuit, said function unit programmed to set a control function of said actuation circuit based upon a state of said output signal.
5. The integrated circuit according to claim 4, wherein said function unit has a self-test unit for analyzing respectively successive states of said output signal, said self-test unit programmed to incrementally set said actuation circuit based upon a result of the analysis.
6. The integrated circuit according to claim 1, wherein said actuation circuit has a control function to be set based on a reference value, and a memory unit for storing said reference value.
7. The integrated circuit according to claim 6, wherein said memory unit has programmable elements.
8. The integrated circuit according to claim 7, wherein said programmable elements are programmable fuses.
9. The integrated circuit according to claim 1, including an oscillator circuit connected to said terminal for producing the digital signal.
10. In a DRAM memory circuit, an integrated circuit comprising:
a terminal for supplying a digital signal;
a controllable driver circuit having a driver input connected to said terminal for receiving the digital signal and a driver output for outputting the digital signal;
an actuating circuit for actuating the driver circuit as a function of a clock signal, said actuating circuit having an actuating input for receiving the clock signal; and
a comparator device having:
a first comparator input for receiving the clock signal;
a second comparator input connected to said driver output for receiving the digital signal; and
a comparator output,
said comparator device outputting, from said comparator output, an output signal having:
a first state if a signal transition of the clock signal at said first comparator input takes place before a signal transition of the digital signal at said second comparator input; and
a second state if the signal transition of the clock signal at said first comparator input takes place after the signal transition of said digital signal at said second comparator input.
11. The integrated circuit according to claim 10, wherein the digital signal includes a data validity signal and a data clock signal for reading out data from the DRAM memory circuit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A frequency multiplier comprising:
a multiphase signal generator configured to generate multiphase signals in response to a source signal;
a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to edges of even numbered signals among the pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to edges of odd numbered signals among the pulse signals,
wherein each of the plurality of pulse signals is generated in response to a corresponding multiphase signal.
2. The frequency multiplier according to claim 1, wherein the source signal comprises a clock signal.
3. The frequency multiplier according to claim 1, wherein the multiphase signal generator comprises:
a delay line configured to delay the source signal by a delay time adjusted in response to a delay control voltage and generate pre-multiphase signals;
a buffer configured to buffer the pre-multiphase signals and generate the multiphase signals;
a phase detector configured to detect a phase difference between two signals among the multiphase signals and generate a phase difference detection signal; and
a charge pump configured to generate the delay control voltage in response to the phase difference detection signal.
4. The frequency multiplier according to claim 3, wherein the phase detector detects a phase difference of the first signal and the last signal among the multiphase signals, and generates the phase difference detection signal.
5. The frequency multiplier according to claim 1, wherein the pulse generator is configured to sequentially respond to the multiphase signals and generate the plurality of pulse signals in which falling pulses and rising pulses are repeated.
6. The frequency multiplier according to claim 1, wherein the pulse generator comprises:
a plurality of falling pulse generation units configured to generate falling pulse signals among the plurality of pulse signals in response to even multiphase signals; and
a plurality of rising pulse generation units configured to generate rising pulse signals among the plurality of pulse signals in response to odd multiphase signals.
7. The frequency multiplier according to claim 6, wherein each of the falling pulse generation units comprises:
an inverter chain configured to receive one of the even multiphase signals and generate an inverted and delayed signal; and
a logic gate configured to receive one of the even multiphase signals and the inverted and delayed signal and generate a falling pulse signal.
8. The frequency multiplier according to claim 7, wherein the falling pulse signal has a pulse width which is set according to a signal delay time of the inverter chain.
9. The frequency multiplier according to claim 6, wherein each of the rising pulse generation units comprises:
an inverter chain configured to receive one of the odd multiphase signals and generate an inverted and delayed signal; and
a logic gate configured to receive one of the odd multiphase signals and the inverted and delayed signal and generate a rising pulse signal.
10. The frequency multiplier according to claim 9, wherein the rising pulse signal has a pulse width which is set according to a signal delay time of the inverter chain.
11. The frequency multiplier according to claim 1, wherein the synthesizer comprises:
a plurality of first switches configured to change the logic level of the frequency multiplication signal to a logic high level in response to first edges of the even numbered signals among the pulse signals; and
a plurality of second switches configured to change the logic level of the frequency multiplication signal to a logic low level in response to second edges of the odd numbered signals among the pulse signals.
12. The frequency multiplier according to claim 11, further comprising a latch configured to latch and output the level-changed frequency multiplication signal.
13. A frequency multiplier comprising:
a multiphase signal generator configured to generate even and odd multiphase signals in response to a source signal;
a falling pulse generation unit configured to generate falling pulse signals in response to the even multiphase signals;
a rising pulse generation unit configured to generate rising pulse signals in response to the odd multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to edges of the falling pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to edges of the rising pulse signals.
14. The frequency multiplier according to claim 13, wherein the multiphase signal generator comprises a delay locked loop.
15. The frequency multiplier according to claim 13, further comprising a latch configured to latch and output the level-changed frequency multiplication signal.
16. A frequency multiplier comprising:
a multiphase generator configured to generate multiphase signals with a predetermined phase difference through a delay time compensation process in response to source signals;
a pulse generator configured to generate a plurality of pulse signals in response to the multiphase signals; and
a synthesizer configured to change a logic level of a frequency multiplication signal to a first logic level in response to falling edges of even numbered signals among the pulse signals, and change the logic level of the frequency multiplication signal to a second logic level in response to rising edges of odd numbered signals among the pulse signals.
17. The frequency multiplier of claim 16, further comprising:
a plurality of delay units configured to delay the source signals by a delay time in response to a delay control voltage.
18. The frequency multiplier of claim 17, further comprising:
a charge pump configured to perform a pumping operation to generate the delay control voltage in response to phase difference detection signals.
19. The frequency multiplier of claim 18, wherein the charge pump may be configured to compensate for a phase difference between a first signal and a last signal to allow the multiphase signals to have a constant delay time.
20. The frequency multiplier of claim 16, wherein the synthesizer is configured to generate the frequency multiplication signal by a multiplication of a frequency to a preset ratio.