1. A method of automatically harvesting and screening plant embryos in multiple stages, comprising:
automatically sorting and singulating plant embryos;
automatically classifying the sorted and singulated plant embryos using a first classification method; and
automatically classifying the plant embryos that have passed the first classification method using a second classification method.
2. The method of claim 1, wherein the step of automatic sorting and singulating comprises automatically removing plant embryos from a development medium.
3. The method of claim 2, wherein the automatic removal of plant embryos comprises washing off the plant embryos from the development medium using aqueous liquid.
4. The method of claim 1, wherein the step of sorting and singulating embryos comprises using a flow cytometer.
5. The method of claim 1, wherein the step of sorting and singulating embryos comprises placing the embryos onto a porous material for sieving.
6. The method of claim 5, wherein the embryos placed on the porous material are sprayed with aqueous liquid to remove any suspensor tissues or residual embryonal suspensor masses (ESM) from the embryos.
7. The method of claim 5, wherein the porous material comprises a porous conveyor belt.
8. The method of claim 7, wherein the embryos are placed in a reservoir which dispense the embryos onto the porous conveyor belt, the reservoir being configured to dispense the embryos onto the belt in a regulated manner.
9. The method of claim 8, wherein the reservoir comprises a pipe.
10. The method of claim 7, wherein the plant embryos sorted and singulated after sieving are placed on a classification conveyor belt, along which the first and second automatic classification methods are carried out.
11. The method of claim 10, wherein the sorted and singulated plant embryos are transferred from the porous conveyor belt to the classification conveyor belt by gravity.
12. The method of claim 10, wherein the classification conveyor belt extends generally perpendicularly to the porous conveyor belt.
13. The method of claim 10, wherein the sorted and singulated plant embryos are placed on the classification conveyor belt in a single file along the length of the classification conveyor belt.
14. The method of claim 13, wherein the plant embryos are placed in a single file spaced apart from each other.
15. The method of claim 10, further comprising the step of automatically removing those embryos that have been classified as undesirable by the first or second automatic classification method from the classification conveyor belt.
16. The method of claim 15, wherein the automatic removal of undesirable embryos is carried out by a jet.
17. The method of claim 10, further comprising the step of automatically removing those embryos that have been classified as desirable by the first and second automatic classification methods from the classification conveyor belt.
18. The method of claim 17, wherein the step of automatically removing desirable embryos comprises transferring those desirable embryos onto a receiving surface in a predefined array.
19. The method of claim 18, wherein the receiving surface comprises a tray mounted on a motorized platform configured to adjust the position of the tray relative to the classification conveyor belt so as to receive the embryos dropping by gravity from the classification conveyor belt into a predefined array.
20. The method of claim 19, wherein the dropping of the embryos by gravity from the classification conveyor belt is assisted by a jet.
21. The method of claim 7, wherein the sorted and singulated plant embryos are classified according to the first classification method while on the porous conveyor belt, and the plant embryos that have passed the first classification method are transferred from the porous conveyor belt onto an index tray in a predefined array.
22. The method of claim 21, wherein the second classification method is carried out on the plant embryos that are placed on the index tray.
23. The method of claim 1, wherein the first classification step classifies the embryos based on their shape and size and the second classification step classifies the embryos based on their putative germination vigor according to a predefined classification model.
24. The method of claim 1, wherein the second classification method is more selective and time-consuming than the first classification method.
25. A system for automatically harvesting and screening plant embryos in multiple stages, comprising:
means for automatically sorting and singulating plant embryos;
means for automatically classifying the sorted and singulated plant embryos using a first classification method; and
means for automatically classifying the plant embryos that have passed the first classification method using a second classification method.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor integrated circuit comprising:
cell arrays comprised of multiple basic cells formed in arrays, wherein each of the basic cells comprises:
an input switch connected to input lines that receive input data only from immediately adjacent upperlowerrightleft basic cells;
a first data path including a first data holding circuit and an arithmetic logic circuit between the input switch and output lines that output data only to the immediately adjacent upperlowerrightleft basic cells;
a second data path including a second data holding circuit between the input switch and the output lines; and
a configuration memory
wherein the input lines and the output lines are each connected only to the immediately adjacent upperlowerrightleft basic cells;
wherein the configuration memory is adapted to store input switch selection information and arithmetic logic circuit function information;
wherein the input switch is adapted to select the input data specified by the input switch selection information from among the input lines;
wherein the arithmetic logic circuit is adapted to perform calculations on the input data as specified by the arithmetic logic circuit function information;
wherein the first data holding circuit is adapted to store calculated result data from the arithmetic logic circuit, and the second data holding circuit is adapted to hold data input from the input lines,
wherein each of the basic cells is adapted to perform an arithmetic calculation by using the first path and to simultaneously transfer data by using the second path in parallel, and
wherein the input switch is adapted to select the input data sent from any of the immediately adjacent upper basic cell, lower basic cell, left basic cell and right basic cell, and to output the selected input data to any of the first data path and the second data path,
wherein the configuration memory comprises a configuration selector, a first configuration memory device and a second configuration memory device;
wherein each of the first configuration memory device and a second configuration memory device is adapted to store the input switch selection information and the arithmetic logic circuit function information,
wherein the configuration selector is adapted to output the input switch selection information and the arithmetic logic circuit function information stored in one of the first configuration memory device and the second configuration memory device into the input switch and the arithmetic logic circuit according to an instruction on a configuration select signal line, and
wherein the input switch selection information and the arithmetic logic circuit function information stored in the unselected one of the first and second configuration memory devices are rewritten while the configuration selector outputs the input switch selection information and the arithmetic logic circuit function information stored in the selected one of the first and second configuration memories.
2. A semiconductor integrated circuit according to claim 1, wherein the arithmetic logic circuit includes a first arithmetic circuit, and a second arithmetic circuit for performing calculations different from the first arithmetic circuit, and
the arithmetic logic circuit is adapted to utilize first arithmetic function information to decide whether to perform arithmetic calculations using the first arithmetic circuit or perform calculations using the second arithmetic circuit.
3. A semiconductor integrated circuit according to claim 1,
wherein either one of the first configuration memory device and a second configuration memory device, which is selected by the configuration select signal line, does allow rewriting.
4. A semiconductor integrated circuit according to claim 3,
wherein the configuration memory further comprises an address decoder, an address signal line and a data line;
wherein the address decoder is adapted to decode addresses on the address line; and
wherein the input switch selection information and the arithmetic logic circuit function information in either one of the first configuration memory device and the second configuration memory device, which matches the address, are rewritten by data input from the data line.
5. A semiconductor integrated circuit according to claim 1, further comprising a controller adapted to control writing of the input switch selection information, on the configuration memory contained in each of the multiple basic cells.
6. A semiconductor integrated circuit according to claim 1, further comprising a data memory adapted to store data for processing, wherein the data stored in the data memory is input to the cell arrays.
7. A semiconductor integrated circuit according to claim 1, wherein each cell further comprises:
a third data path between the input switch and the output lines,
wherein the third data path is adapted to transfer data input from the input lines into the output lines.
8. A semiconductor integrated device according to claim 1, further comprising:
a third data path connected between an input of the input switch and an output of the first data holding circuit; and
a fourth data path connected between the input of the input switch and an output of the second data holding circuit,
wherein the input switch is adapted to select the input data sent from any of the immediately adjacent upper basic cell, the lower basic cell, left basic cell and right basic cell and the third and the fourth paths, and to output the selected input data to any of the first data path and the second data path.