1. A hydrocyanic acid, characterized in that it comprises a content by weight of 14C such that the 14C12C ratio is between 0.2\xd710\u221212 and 1.2\xd710\u221212 according to the standard ASTM D 6866.
2. A process for the synthesis of hydrocyanic acid by reaction of ammonia with methane or methanol, optionally in the presence of air andor of oxygen, characterized in that at least one of said ammonia, methane or methanol is obtained from biomass.
3. The process as claimed in claim 2, characterized in that the ammonia is obtained from hydrogen resulting from a syngas (COH2) resulting from the gasification of biomass.
4. The process as claimed in claim 2, characterized in that the methane is obtained from biogas (CH4CO2) produced by the fermentation of animal or vegetable organic matter in the absence of oxygen, the CO2 being removed by washing the biogas using a basic aqueous sodium hydroxide, potassium hydroxide or amine solution or with water under pressure or by absorption in a solvent.
5. The process as claimed in claim 2, characterized in that the methanol is obtained from the pyrolysis of wood.
6. The process as claimed in claim 2, characterized in that the methanol is obtained by fermentation of crops of plants.
7. The process as claimed in claim 2, characterized in that the methanol is obtained by gasification of any material of animal or vegetable origin, resulting in a syngas composed essentially of carbon monoxide and hydrogen which is reacted with water.
8. The process as claimed in claim 7, characterized in that the syngas results from spent liquor from the manufacture of cellulose pulps.
9. The process as claimed in claim 2, characterized in that ammonia is reacted with methane in the presence of air and optionally of oxygen over a catalyst composed of rhodiumplatinum gauzes at a temperature ranging from approximately 1050-1150\xb0 C.
10. The process as claimed in claim 2, characterized in that ammonia is reacted with methanol at a temperature ranging from 350\xb0 C. to 600\xb0 C. in the presence of a catalyst.
11-14. (canceled)
15. A method of producing a hydrocyanic acid selected from the group consisting of acetone cyanohydrin, adiponitrile, methionine, methionine hydroxy analogue and sodium cyanide comprising reacting ammonia with methane or methanol, optionally in the presence of air andor of oxygen, wherein at least one of said ammonia, methane or methanol is obtained from biomass.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of forming a nonvolatile memory integrated circuit comprising:
depositing a floating gate layer of doped polysilicon across a cell area and across a peripheral area of a substrate;
depositing an inter-poly dielectric layer over the floating gate layer in the cell area and in the peripheral area of the substrate;
depositing a P+ doped polysilicon layer over the inter-poly dielectric layer in the cell area and in the peripheral area of the substrate;
forming a plurality of openings in the P+ doped polysilicon layer and the inter-poly dielectric layer in the peripheral area of the substrate;
depositing an N+ doped polysilicon layer over the P+ doped polysilicon layer in the cell area and in the peripheral area of the substrate, the N+ doped polysilicon layer deposited to at least a minimum thickness over the P+ doped polysilicon layer that is sufficient to maintain N+ doping at an upper surface of the N+ doped polysilicon layer;
subsequently masking the peripheral area of the substrate while leaving the cell area exposed;
subsequently removing material of the N+ doped polysilicon layer from the cell area while leaving the N+ doped polysilicon layer in place in the peripheral area; and
subsequently depositing a metal layer over the P+ doped polysilicon layer in the cell area and over the upper surface of the N+ doped polysilicon layer in the peripheral area, a first contact resistance between the metal layer and the upper surface of the N+ doped polysilicon layer being less than a second contact resistance along an interface between the P+ doped polysilicon layer and the metal layer in the cell area.
2. The method of claim 1 wherein the removing material of the N+ doped polysilicon layer from the cell area removes less than all material of the N+ doped polysilicon layer from the cell area.
3. The method of claim 1 wherein the material of the N+ doped polysilicon layer is removed from the cell area using an etch that also removes at least some material of the P+ doped polysilicon layer.
4. The method of claim 1 wherein the N+ doped polysilicon layer is deposited directly on the floating gate layer in the plurality of openings.
5. The method of claim 4 further comprising forming a plurality of peripheral transistors where the plurality of openings are located, a gate of a peripheral transistor formed thru a portion of the floating gate layer, a portion of the P+ doped polysilicon layer, and a portion of the N+ doped polysilicon layer in electrical contact.
6. The method of claim 1 further comprising:
subsequent to removing material of the N+ doped polysilicon layer from the cell area, unmasking the peripheral area of the substrate
prior to depositing the metal layer in the cell area and in the peripheral area.
7. The method of claim 6 further comprising:
subsequent to depositing the metal layer, patterning the cell area to form floating gates from the floating gate layer and to form control gates from the P+ doped polysilicon layer and the metal layer.
8. The method of claim 1 further comprising forming additional openings in the P+ doped polysilicon layer and the inter-poly dielectric layer in the cell area and subsequently forming select transistors at locations of the additional openings.
9. A method of forming a nonvolatile memory integrated circuit comprising:
depositing a gate dielectric layer across a cell area and across a peripheral area of a substrate;
depositing a floating gate layer over the gate dielectric layer in the cell area and in the peripheral area of the substrate;
depositing an inter-poly dielectric layer over the floating gate layer in the cell area and in the peripheral area of the substrate;
depositing a first control gate polysilicon layer over the inter-poly dielectric layer in the cell area and in the peripheral area of the substrate;
forming a plurality of openings in the first control gate polysilicon layer and the inter-poly dielectric layer in the peripheral area of the substrate;
depositing a second control gate polysilicon layer over the first control gate polysilicon layer in the cell area and in the peripheral area of the substrate so that the second control gate polysilicon layer contacts the floating gate layer in the plurality of openings;
subsequently removing material of the second control gate polysilicon layer from the cell area while leaving the second control gate polysilicon layer intact in the peripheral area; and
subsequently depositing a metal control gate layer in the cell area and in the peripheral area of the substrate.
10. The method of claim 9 wherein the first control gate polysilicon layer is formed of P+ doped polysilicon and the second control gate polysilicon layer is deposited as undoped polysilicon and is subsequently selectively implanted with N-type dopant in only the peripheral area.