What is claimed is:
1. A second base station for use in a second communications cell located adjacent a first communications cell in which a first base station transmits first and second carrier signals, the first carrier signal having a first frequency with communication bandwidth, second carrier signal having a second carrier frequency with communications bandwidth, the second carrier frequency being different from the first carrier frequency, a first amount of power being allocated by the first base station for transmitting the first carrier signal and a second amount of power being allocated by the first base station to transmit the second carrier signal, the first amount of power being less than the second amount of power, the second base station comprising:
means for transmitting third and fourth carrier signals, the third carrier signal having the same carrier frequency as said first carrier signal, the fourth carrier signal have the same carrier frequency as said second carrier signal; and
means for allocating the transmission power to the third and fourth carrier signals to maintain a power difference between said third and fourth carrier signals, the transmission power allocated to the third carrier signal being greater than the transmission power allocated to the fourth carrier signal.
2. The second base station of claim 1,
wherein the difference between the power of the first and second carrier signals and the difference in power between the third and fourth power signals is sufficiently large to insure that there is less than a 50 percent over lap in a first boundary region corresponding to interference between the first and third carrier signals and a second boundary region corresponding to interference between the second and fourth carrier signals; and
wherein the first boundary region between said first and third carrier signals corresponds to a region where there is less than a 3 dB difference between the power of the first and third carrier signals.
3. The base station of claim 2, wherein there is no overlap between the first and second boundary regions.
4. The second base station of claim 2, wherein the means for controlling the transmission power maintains a transmission power difference of at least 20 percent, on average, between the third and fourth carrier signals.
5. The second base station of claim 4, where the means for controlling the transmission power maintains the transmission power of level of said third carrier signal to be approximately equal to the transmission power level of the second carrier signal; and maintains the transmission power level of said fourth carrier signal to be approximately equal to the transmission power level of the first carrier signal.
6. The second base station of claim 1, wherein the second base station further comprises:
means for allocating communications bandwidth of at least one of said third and fourth carrier signals to a wireless terminal as a function of information indicating whether the wireless terminal is in a non-boundary region, a first boundary region between said first and third carrier signals or a second boundary region between said second and fourth carrier signals.
7. The second base station of claim 6, wherein said first base station includes means for allocating communications bandwidth corresponding to the second carrier when said information indicates that said wireless terminal is in said first boundary region.
8. The second base station of claim 6, wherein said means for allocating communications bandwidth allocates communications bandwidth corresponding to the third carrier when said information indicates that said wireless terminal is in said second boundary region.
9. The second base station of claim 6, wherein said means for allocating communications bandwidth allocates communications bandwidth corresponding to one of either said third and fourth carrier when said information indicates that said wireless terminal is in a non-boundary region.
10. The second base station of claim 6, further comprising:
means for receiving intercell interference information and intracell interference information from a wireless terminal and determining from said received information whether the wireless terminal is in a boundary region or a non-boundary region.
11. The second base station of claim 10, wherein said intercell interference information and intracell interference information are included in channel quality information received from said wireless terminal.
12. The second base station of claim 6, wherein said means for allocating communication bandwidth allocates communications bandwidth to a wireless terminal from the third carrier when said wireless terminal enters an intercell boundary region corresponding to said second and fourth carrier signals, said allocating causing an intercarrier handoff within said base station prior to said wireless terminal encountering an unacceptable level of signal interference when using said fourth carrier signal.
13. The method of claim 12, wherein said unacceptable level of signal interference occurs when a power level of an interference signal is 80% or more of a power level of a signal of interest.
14. A communications cell, comprising:
a base station including:
i. means for transmitting a different first carrier signal into each of a first set of sectors of said cell, each of the different first carrier signals having a first carrier frequency which is the same; and
ii. means for transmitting a different second carrier signal into each of a second set of sectors of said cell, each of the different second carrier signals having a second carrier frequency which is different from the first carrier frequency, said first and second sets of sectors overlapping but having sector boundaries which are offset from one another.
15. The communications cell of claim 14, wherein said first set of sectors includes sector boundaries which are offset from sector boundaries of said second set of sectors by at least 10 degrees.
16. The communications cell of claim 15, wherein each of the first and second sets of sectors include 3 sectors and wherein the sector boundaries of the first set of sectors are offset from the sector boundaries of the second set of sectors by 60 degrees.
17. The communications cell of claim 15,
means for determining from information received from a wireless terminal whether said wireless terminal is located in a sector boundary area corresponding to the first carrier frequency, a sector boundary area corresponding to the second carrier frequency or a non-sector boundary area; and
means for allocating communications bandwidth to said wireless terminal as a function of determined boundary area information, said means for allocating communications bandwidth allocating communications bandwidth corresponding to one of said different second carrier signals when said wireless terminal is determined to be in a sector boundary area corresponding to the first carrier frequency.
18. The communications cell of claim 17, wherein said means for allocating communications bandwidth allocates communications bandwidth corresponding to one of said different first carrier signals to said wireless terminal when said wireless terminal is determined to be in a sector boundary area corresponding to the second carrier frequency.
19. The communications cell of claim 17, wherein said means for allocating communications bandwidth allocates communications bandwidth corresponding to one of said first and second carrier signals to said wireless terminal when said wireless terminal is determined to be in a non-sector boundary area, said allocating being performed as a function of first and second carrier loading information relating to the sector in which said wireless terminal is located.
20. The communications cell of claim 17, wherein said means for allocating communications bandwidth allocates communications bandwidth corresponding to different ones of said first and second carrier signals to a wireless terminal in a sector causing an intracell intersector intercarrier handoff, said intracell intersector intercarrier carrier handoff being performed while said wireless terminal is still able to reliably communicate with the base station using the carrier which will no longer be used by the wireless terminal following the handoff.
21. The communications cell of claim 20, wherein the handoff occurs while signal interference power level remains below 80% of the power level of the carrier which will no longer be used.
22. The communications cell of claim 20, wherein said means for allocating communications bandwidth allocates communications bandwidth evaluates feedback information received from a wireless terminal to determine which carrier frequency would be best for transmitting data to said wireless terminal and completes an in intracell intersector intercarrier handoff when it is determined that a carrier frequency other than the one currently being used to communicate with said wireless terminal would be better suited for such communication.
23. The communications cell of claim 22, wherein said intracell intersector intercarrier handoff is performed at least once while the carrier frequency being used to communicate data to said wireless terminal provides a satisfactory signal to noise ratio.
24. A method of operating a wireless terminal in a cell which includes a basestation which transmits at least two carrier signals at different power levels, the said at least two different carrier signal including a first carrier signal having a first carrier frequency and a second carrier signal having a second carrier frequency, the method comprising:
operating said wireless terminal to communicate with said base station using said first carrier signal over a period of time;
during said period of time, checking a plurality of said transmitted carrier signals to determine channel interference associated with each of said carrier signals; and
initiating an intercarrier handoff between carrier signals used by said base station, while said first carrier signal still provides a signal to noise ration of at least 0 dB and another one of said carrier signals is subject to lower channel interference.
25. The method of claim 24, wherein said wireless terminal estimates intercell channel interference due to transmissions from another base station and wherein said intercarrier handoff is intiated to cause an intercarrier handoff to a carrier subject to lower intercell interference in the geographic region in which said wireless terminal is located.
26. The method of claim 24, wherein said intercarrier handoff is triggered by detecting a decrease in the first carrier signal’s signal to noise ratio.
27. The method of claim 24, wherein said wireless terminal estimates intersector channel interference due to transmissions from another sector of said base station and wherein said intercarrier handoff is initiated to cause an intercarrier handoff to a carrier subject to lower intersector interference in the geographic region in which said wireless terminal is located.
28. A wireless terminal, comprising:
receiver means for receiving carrier signals corresponding to at least two different available carrier frequencies transmitted by the same base station;
carrier selection means for selecting which one of said different available carrier frequencies to use at any point in time for the receipt of information, said carrier frequency selecting means including:
means for repeatedly checking, during an interval of time during which said wireless terminal has a reliable communications connection with said base station using a first one of the available carrier frequencies, which of the available carrier frequencies has better interference properties; and
means for signaling the base station to initiate an intracell intercarrier handoff to change the carrier frequency used to communicate with the wireless terminal when on of the available carrier frequencies is determined to be better for communication of signals to said wireless terminal than the carrier frequency being used.
29. The wireless terminal of claim 28, wherein said intracell carrier handoff is an intersector handoff.
30. The wireless terminal of claim 28, wherein said means for checking performs said checking operation irrespective of the signal quality of a carrier signal being used for an ongoing communication session.
31. The wireless terminal of claim 28, wherein said wireless terminal includes:
means for distinguishing between intracell interference and other types of interference.
32. The wireless terminal of claim 28, wherein said wireless terminal includes:
means for distinguishing between intersector interference and other types of interference.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method for fabricating a transistor, the method comprising:
providing a silicon layer above a substrate, the silicon layer being separated from the substrate by one or more layers;
forming a first layer on and in contact with the silicon layer, the first layer comprising a high dielectric constant material;
forming a second layer and in contact with the first layer, the second layer comprising a metal or metal alloy;
forming a third layer on the second layer, the third layer comprising silicon or polysilicon;
etching the first, second, and third layers so as to form first, second, and third layers of a gate stack;
depositing an encapsulation layer, the encapsulation layer including a horizontal portion in contact with the silicon layer and a vertical portion that is located on and in contact with sidewalls of the gate stack;
after depositing the encapsulation layer, depositing one spacer layer above and in contact with the horizontal portion of the encapsulation layer and adjacent to and in contact with the vertical portion of the encapsulation layer,
wherein depositing the one spacer layer comprises
depositing a first spacer layer above the horizontal portion of the encapsulation layer and adjacent to the vertical portion of the encapsulation layer, and
after depositing the first spacer layer, depositing a second spacer layer;
after depositing the spacer layer, etching the encapsulation layer and the one spacer layer so as to form a spacer and an L-shaped gate encapsulation layer that is disposed on the sidewalls of the gate stack, the L-shaped gate encapsulation layer comprising a vertical portion covering and in contact with the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering and in contact with a portion of the silicon layer that is adjacent to the gate stack, and the spacer being above and in contact with the horizontal portion of the L-shaped gate encapsulation layer and adjacent to and in contact with the vertical portion of the L-shaped gate encapsulation layer, the spacer extending from the vertical portion of the L-shaped gate encapsulation layer to the horizontal portion of the L-shaped gate encapsulation layer, the spacer comprising a vertical sidewall extending from a surface of the horizontal portion of the L-shaped gate encapsulation layer to a height above at least the second layer comprising the metal or metal alloy,
wherein etching the encapsulation layer and the at least one spacer layer further comprises
etching the first spacer layer and the second spacer layer so as to form the spacer, the spacer further comprising:
an L-shaped spacer layer that includes a vertical portion covering sidewalls of the vertical portion of the L-shaped gate encapsulation layer, and a horizontal portion covering the horizontal portion of the L-shaped gate encapsulation layer, where the L-shaped spacer layer is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer; and
the second spacer layer disposed on sidewalls of the vertical portion of the L-shaped oxide layer and above the horizontal portion of the L-shaped oxide layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the second spacer layer are formed with a combined width that is greater than a width of the gate stack;
after etching the encapsulation layer and the one spacer layer, performing an extension implantation to implant ions so as to form sourcedrain extensions in the silicon layer, the sourcedrain extensions not underlying the gate stack; and
after performing the extension implantation, performing a sourcedrain implantation and performing an anneal to implant and diffuse ions for source and drain regions in the silicon layer,
wherein the extension implantation and the sourcedrain implantation are two separate implantations, and
both the extension implantation and the sourcedrain implantation are performed after etching the encapsulation layer and the one spacer layer and while the spacer is present above the horizontal portion of the L-shaped gate encapsulation layer and adjacent to the vertical portion of the L-shaped gate encapsulation layer.
2. The method of claim 1, wherein a thickness of the L-shaped gate encapsulation layer is less than a thickness of the first layer of the gate stack.
3. The method of claim 1, wherein a thickness of the vertical portion of the L-shaped gate encapsulation layer is substantially equal to a thickness of the horizontal portion of the L-shaped gate encapsulation layer.
4. The method of claim 1, wherein depositing the encapsulation layer comprises performing molecular layer deposition (MLD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or rapid thermal chemical vapor deposition (RTCVD) to deposit a layer of nitride.
5. The method of claim 1, wherein the first spacer layer is an oxide layer, and where the second spacer layer is a nitride layer.
6. The method of claim 1, wherein the horizontal portion of the L-shaped gate encapsulation layer directly contacts the silicon layer.
7. The method of claim 1, wherein depositing an encapsulation layer is performed after etching the first, second, and third layers.
8. The method of claim 1, wherein portions of the source and drain regions underlie the spacer.
9. The method of claim 1, wherein etching the first, second, and third layers comprises performing a single etch that etches the first, second, and third layers and stops on the silicon layer, so as to form the gate stack in the single etch.
10. The method of claim 1, wherein the L-shaped gate encapsulation layer consists of a single layer.
11. The method of claim 1,
wherein the L-shaped gate encapsulation layer consists of a single encapsulation layer, the spacer consists of a single spacer layer, and
the single spacer layer of the spacer directly contacts the single encapsulation layer of the L-shaped gate encapsulation layer.
12. The method of claim 1,
wherein
the first spacer layer consists of SiO2.
13. The method of claim 1,
wherein
the first spacer layer does not comprise a high dielectric constant material and the second spacer layer comprises a nitride layer.
14. A non-transitory computer readable storage medium encoded with a program for fabricating a nFET transistor and a pFET transistor, the program comprising instructions for performing:
providing a buried oxide layer on and in contact with a single substrate, where the single substrate comprises an nFET region and a pFET region;
providing a silicon layer on and in contact with the buried oxide layer, the silicon layer being provided across both the nFET and pFET regions of the substrate;
depositing a silicon germanium layer on and in contact with the silicon layer;
forming a first layer on and in contact with the silicon germanium layer, the first layer comprising a high dielectric constant material, the first layer being provided across both the nFET and pFET regions of the substrate;
forming a second layer on and in contact with the first layer, the second layer comprising a metal or metal alloy and being provided across both the nFET and pFET regions of the substrate;
forming a third layer on the second layer, the third layer comprising silicon or polysilicon and being provided across both the nFET and pFET regions of the substrate;
etching the first, second, and third layers so as to form first, second, and third layers of a first gate stack in the nFET region and first, second, and third layers of a second gate stack in the pFET region;
depositing a nitride encapsulation layer, the nitride encapsulation layer including a horizontal portion in contact with the silicon layer and a vertical portion that is located on and in contact with sidewalls of the first and second gate stacks;
after depositing the nitride encapsulation layer, depositing at least one spacer layer above and in contact with the horizontal portion of the nitride encapsulation layer and adjacent to and in contact with the vertical portion of the nitride encapsulation layer,
wherein depositing the one spacer layer comprises
depositing a first spacer layer above the horizontal portion of the encapsulation layer and adjacent to the vertical portion of the encapsulation layer, and
after depositing the first spacer layer, depositing a second spacer layer;
after depositing the at least one spacer layer, etching the nitride encapsulation layer and the at least one spacer layer as part of a single etch, the etching forming a first spacer and a first L-shaped gate encapsulation layer that is disposed on the sidewalls of the first gate stack in the nFET region and a second spacer and a second L-shaped gate encapsulation layer that is disposed on the sidewalls of the second gate stack in the pFET region, the first and second L-shaped gate encapsulation layers each comprising a vertical portion covering the sidewalls of the first, second, and third layers of the first and second gate stacks, respectively, and a horizontal portion covering a portion of the silicon layer that is adjacent to the first and second gate stacks, respectively, and each of the first and second spacers being above and in contact with the horizontal portion of the first and second L-shaped gate encapsulation layers, respectively, and adjacent to and in contact with the vertical portion of the first and second L-shaped gate encapsulation layers, respectively, each of the first and second spacers extending from the vertical portion of the first and second L-shaped gate encapsulation layers, respectively, to the horizontal portion of the first and second L-shaped gate encapsulation layers, respectively, each of the first and second spacers comprising a vertical sidewall extending from a surface of the horizontal portion of the first and second L-shaped gate encapsulation layers, respectively, to a height above at least the second layer comprising the metal or metal alloy,
wherein etching the encapsulation layer and the at least one spacer layer further comprises
etching the first spacer layer and the second spacer layer so as to form the spacer, the spacer further comprising:
an L-shaped spacer layer that includes a vertical portion covering sidewalls of the vertical portion of the L-shaped gate encapsulation layer, and a horizontal portion covering the horizontal portion of the L-shaped gate encapsulation layer, where the L-shaped spacer layer is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer; and
the second spacer layer disposed on sidewalls of the vertical portion of the L-shaped oxide layer and above the horizontal portion of the L-shaped oxide layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the second spacer layer are formed with a combined width that is greater than a width of the gate stack;
after etching the nitride encapsulation layer and the at least one spacer layer, performing an extension implantation to implant ions so as to form sourcedrain extensions in the silicon layer, the sourcedrain extensions not underlying the first and second gate stacks; and
after performing the extension implantation, performing a sourcedrain implantation and performing an anneal to implant and diffuse ions for source and drain regions in the silicon layer,
wherein the extension implantation and the sourcedrain implantation are two separate implantations, and
both the extension implantation and the sourcedrain implantation are performed after etching the nitride encapsulation layer and the at least one spacer layer and while the first and second are present above the horizontal portion of the first and second L-shaped gate encapsulation layers, respectively, and adjacent to the vertical portion of the L-shaped gate encapsulation layers, respectively.
15. The non-transitory computer readable storage medium of claim 14, wherein a thickness of the first and second L-shaped gate encapsulation layers, respectively, is less than a thickness of the first layer of the gate stack.
16. The non-transitory computer readable storage medium of claim 14, wherein a thickness of the vertical portion of the first and second L-shaped gate encapsulation layers, respectively, is substantially equal to a thickness of the horizontal portion of the first and second L-shaped gate encapsulation layers, respectively.
17. The non-transitory computer readable storage medium of claim 14, wherein depositing the nitride encapsulation layer comprises performing molecular layer deposition (MLD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), or rapid thermal chemical vapor deposition (RTCVD) to deposit a layer of nitride.
18. A method for fabricating a transistor, the method comprising:
providing a silicon layer above a substrate, the silicon layer being separated from the substrate by one or more layers;
forming a first layer on and in contact with the silicon layer, the first layer comprising a high dielectric constant material;
forming a second layer on and in contact with the first layer, the second layer comprising a metal or metal alloy;
forming a third layer on the second layer, the third layer comprising a conducting metal;
etching the first, second, and third layers so as to form first, second, and third layers of a gate stack;
depositing an encapsulation layer, the encapsulation layer including a horizontal portion in contact with the silicon layer and a vertical portion that is located on and in contact with sidewalls of the gate stack;
after depositing the encapsulation layer, depositing at least one spacer layer above and in contact with the horizontal portion of the encapsulation layer and adjacent to and in contact with the vertical portion of the encapsulation layer,
wherein depositing the one spacer layer comprises
depositing a first spacer layer above the horizontal portion of the encapsulation layer and adjacent to the vertical portion of the encapsulation layer, and
after depositing the first spacer layer, depositing a second spacer layer;
after depositing the at least one spacer layer, etching the nitride encapsulation layer and the at least one spacer layer so as to form a spacer and an L-shaped gate encapsulation layer that is disposed on the sidewalls of the gate stack, the L-shaped gate encapsulation layer comprising a vertical portion covering and in contact with the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering and in contact with a portion of the silicon layer that is adjacent to the gate stack, and the spacer being above and in contact with the horizontal portion of the L-shaped gate encapsulation layer and adjacent to and in contact with the vertical portion of the L-shaped gate encapsulation layer, the spacer extending from the vertical portion of the L-shaped gate encapsulation layer to the horizontal portion of the L-shaped gate encapsulation layer, the spacer comprising a vertical sidewall extending from a surface of the horizontal portion of the L-shaped gate encapsulation layer to a height above at least the second layer comprising the metal or metal alloy,
wherein etching the encapsulation layer and the at least one spacer layer further comprises
etching the first spacer layer and the second spacer layer so as to form the spacer, the spacer further comprising:
an L-shaped spacer layer that includes a vertical portion covering sidewalls of the vertical portion of the L-shaped gate encapsulation layer, and a horizontal portion covering the horizontal portion of the L-shaped gate encapsulation layer, where the L-shaped spacer layer is formed with a thickness that is less than a thickness of the L-shaped gate encapsulation layer; and
the second spacer layer disposed on sidewalls of the vertical portion of the L-shaped oxide layer and above the horizontal portion of the L-shaped oxide layer, wherein the L-shaped gate encapsulation layer, the L-shaped spacer layer, and the second spacer layer are formed with a combined width that is greater than a width of the gate stack;
after etching the encapsulation layer and the at least one spacer layer, performing an extension implantation to implant ions so as to form sourcedrain extensions in the silicon layer, the sourcedrain extensions not underlying the gate stack; and
after performing the extension implantation, performing a sourcedrain implantation and performing an anneal to implant and diffuse ions for source and drain regions in the silicon layer,
wherein the extension implantation and the sourcedrain implantation are two separate implantations, and
both the extension implantation and the sourcedrain implantation are performed after etching the encapsulation layer and the at least one spacer layer and while the spacer is present above the horizontal portion of the L-shaped gate encapsulation layer and adjacent to the vertical portion of the L-shaped gate encapsulation layer.
19. The method of claim 18, wherein the third layer comprises tungsten or aluminum.
20. The method of claim 18, wherein the horizontal portion of the L-shaped gate encapsulation layer directly contacts the silicon layer.