1. A method of enhanced jitter rejection and drift-following while decoding a limited run length encoded signal, the method including:
creating and maintaining in real time using an electronic device a time-varying histogram of transitions in the limited run length encoded signal; and
decoding the limited run length encoded signal with the electronic device, using an absence of transitions falling in particular bins of the histogram to demark one or more boundaries between single and double length intervals among transitions, whereby the decoding proceeds without a need for synchronization within a frame between source and decoder clocks.
2. The method of claim 1, wherein the limited run length encoded signal includes a triple length interval among transitions, in addition to the single and double length intervals, further including using the absence of transitions in the particular bins to demark the boundaries between the double and triple length intervals among transitions.
3. The method of claim 1, wherein the decoding recovers a magnitude of a sample from the frame.
4. The method of claim 1, wherein the limited run length encoded signal uses a biphase mark code compliant with a standard for a SPDIF interface and the decoding recovers magnitudes of audio samples.
5. The method of claim 1, wherein the limited run length encoded signal is compliant with an AES3 interface standard and the decoding recovers magnitudes of audio samples.
6. The method of claim 1, wherein the limited run length encoded signal uses a Manchester code and the decoding recovers data from the Manchester code signal.
7. The method of claim 1, wherein the time-varying histogram of transitions is maintained in a series of registers that are incremented when a transition falls into a time slot represented by the register and decremented with a frequency proportional to a value stored in the register.
8. The method of claim 7, wherein a set of lines correspond to bits in the registers, further including decrementing a particular register when a line corresponding to a bit in the particular register is active and the corresponding bit in the particular register has a \u201c1\u201d value.
9. The method of claim 8, further including activating the lines orthogonally, only one line per clock pulse, and activating particular lines at a rate proportional to their magnitude in the registers, whereby the line corresponding to the most significant bit is activated at least as often as all of the lines corresponding to the less significant bits, combined.
10. An decoder device that rejects jitter while decoding a limited run length encoded signal, the device including:
an input that receives a limited run length encoded signal having transitions separated by at least single and double length intervals;
a clock running at least four times the frequency of a single length interval;
a histogram array coupled to the input and the clock that includes:
a series of registers representing a histogram of transitions in the limited run length encoded signal;
first logic that increments a register index responsive to the clock;
second logic, coupled to the series of registers and the register index, that responds to detection of a next transition by,
incrementing a value in a particular register corresponding to the register index and
resetting the register index;
third logic coupled to the clock and the series of registers that decrements respective registers with a frequency proportional to values in the respective registers; and
decoder logic, responsive to the clock and the next transition and coupled the input and the binary weighted frequency array, that uses the binary weighted frequency array to discriminate between the single and double length intervals among the transitions.
11. The device of claim 10, wherein the third logic includes a set of lines correspond to bits in the registers and logic that decrements a particular register when a line corresponding to a bit in the particular register is active and the corresponding bit in the particular register has a \u201c1\u201d value.
12. The device of claim 11, wherein the third logic further includes logic that activates the lines orthogonally, only one line per clock pulse, and activates particular lines at a rate proportional to a magnitude of the corresponding bit in the registers, so that the line corresponding to the most significant bit is activated at least as often as all of the lines corresponding to the less significant bits, combined.
13. A non-transitory machine readable storage media recording computer instructions adapted to enhanced jitter rejection and drift-following while decoding a limited run length encoded signal, the computer instructions including instructions to:
create and maintain in real time a time-varying histogram of transitions in the limited run length encoded signal; and
decode the limited run length encoded signal, using an absence of transitions falling in particular bins of the histogram to demark one or more boundaries between single and double length intervals among transitions, whereby the decoding proceeds without a need for synchronization within a frame between source and decoder clocks.
14. The non-transitory machine readable storage media of claim 13, wherein the limited run length encoded signal includes a triple length interval among transitions, in addition to the single and double length intervals, further including instructions to use the absence of transitions in the particular bins to demark the boundaries between the double and triple length intervals among transitions.
15. A non-transitory computer readable storage media, recording computer instructions adapted to configure a programmable logic array device, including at least an FPGA, or to generate a cell design in a custom integrated circuit device, the resulting device providing enhanced jitter rejection and drift-following while decoding a limited run length encoded signal, the computer instructions including instructions to:
create and maintain in real time a time-varying histogram of transitions in the limited run length encoded signal; and
decode the limited run length encoded signal, using an absence of transitions falling in particular bins of the histogram to demark one or more boundaries between single and double length intervals among transitions, whereby the decoding proceeds without a need for synchronization within a frame between source and decoder clocks.
16. The non-transitory computer readable storage media of claim 15, wherein the limited run length encoded signal includes a triple length interval among transitions, in addition to the single and double length intervals, further including instructions to use the absence of transitions in the particular bins to demark the boundaries between the double and triple length intervals among transitions.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A structure for measuring misalignment of patterns, comprising:
a first wiring including a first lower pattern and a first upper pattern, the first upper pattern extending in a y-direction, a first end portion of the first upper pattern that is proximal to a negative y-direction contacting the first lower pattern; and
a second wiring including a second lower pattern and a second upper pattern, the second upper pattern extending in the y-direction, a second end portion of the second upper pattern that is proximal to a positive y-direction contacting the second lower pattern, and the second wiring being spaced apart from the first wiring in the negative y-direction.
2. The structure of claim 1, wherein
the first wiring has a first resistance which changes according to a first misalignment between the first upper pattern and the first lower pattern in the y-direction, and
the second wiring has a second resistance which changes according to a second misalignment between the second upper pattern and the second lower pattern in the y-direction.
3. The structure of claim 2, wherein the first resistance increases when the second resistance decreases.
4. A structure for measuring misalignment of patterns, comprising:
a first wiring including a first lower pattern and a first upper pattern, the first upper pattern extending in a y-direction and contacting the first lower pattern;
a second wiring including a second lower pattern and a second upper pattern, the second upper pattern extending in the y-direction and contacting the second lower pattern, the second wiring being spaced apart from the first wiring in a negative y-direction;
two first parallel lines extending in an x-direction perpendicular to the y-direction, each of the first parallel lines having a first tab, the first wiring being between the two first parallel lines; and
two second parallel lines extending in the x-direction, each of the second parallel lines having a second tab, the second wiring being between the two second parallel lines,
wherein a first end portion of the first upper pattern that is proximal to a positive y-direction overlaps the first tab, and a second end portion of the second upper pattern that is proximal to the negative y-direction overlaps the second tab.
5. The structure of claim 4, wherein
the first lower pattern includes a first self-aligned contact plug and the first upper pattern includes a first capacitor contact plug, and
the second lower pattern includes a second self-aligned contact plug and the second upper pattern includes a second capacitor contact plug.
6. The structure of claim 5, wherein the first and second parallel lines include bit lines, and the first and second tabs include bit line tabs.
7. The structure of claim 4, wherein
the first wiring has a first resistance which changes according to a first misalignment between the first upper pattern and the first lower pattern in the y-direction, and
the second wiring has a second resistance which changes according to a second misalignment between the second upper pattern and the second lower pattern in the y-direction.
8. The structure of claim 7, wherein the first resistance increases when the second resistance decreases.
9. A structure for measuring misalignment of patterns, comprising:
a first wiring including a first lower pattern and a first upper pattern, the first lower pattern extending in a y-direction, a first end portion of the first lower pattern that is proximal to a positive y-direction contacting the first upper pattern; and
a second wiring including a second lower pattern and a second upper pattern, the second lower pattern extending in the y-direction, a second end portion of the second lower pattern that is proximal to a negative y-direction contacting the second upper pattern, and the second wiring being spaced apart from the first wiring in the negative y-direction.
10. The structure of claim 9, wherein
the first lower pattern includes a first capacitor contact plug and the first upper pattern includes a first storage node electrode of a first capacitor, and
the second lower pattern includes a second capacitor contact plug and the second upper pattern includes a second storage node electrode of a second capacitor.
11. The structure of claim 10, further comprising:
a first self-aligned contact plug electrically connected to the first capacitor contact plug and a second self-aligned contact plug electrically connected to the second capacitor contact plug.
12-20. (canceled)