1. An information processor comprising:
a storage module configured to store a plurality of pieces of setting information of a plurality of operation modes, respectively, corresponding to a basic inputoutput system (BIOS) setup item;
a setting module configured to acquire one of the pieces of setting information of selected one of the operation modes from the storage module during power on self-test (POST) process by a BIOS, to set the one of the pieces of the setting information to the BIOS during the POST process, and to perform a process corresponding to the set one of the pieces of the setting information during the POST process; and
an input module configured to receive a save request for saving the one of the pieces of the setting information set by the setting module and a restart request for restarting the information processor, wherein
the storage module is configured to store therein, during the POST process, the one of the pieces of the setting information according to the save request so that the one of the operation modes associated with the one of the pieces of the setting information is enabled when the information processor is not in operation, and
the setting module is configured to stop performing the process during the POST process when the input module receives the restart request.
2. The information processor of claim 1, wherein
the operation modes differ from each other and are capable of operating different external devices in different states,
during the POST process by the BIOS, the setting module is configured to acquire the one of the pieces of the setting information of the selected one of the operation modes from the storage module, to set the acquired one of the pieces of the setting information to the BIOS, and to operate the external device in a state corresponding to the acquired one of the operation modes.
3. The information processor of claim 2, further comprising:
the input module configured to receive a setting request of the acquired one of the operation modes, and wherein
the setting module is configured to operate, upon receipt of the setting request of the acquired one of the operation modes by the input module, the device in a state corresponding to the acquired one of the operation modes.
4. An information processor comprising:
an executing module configured to charge one of a plurality of external devices connected to the information processor by one of a plurality of charging modes for charging the external devices, respectively, when the operating system is not in operation, wherein the charging modes comprise at least a first charging mode for charging one of the external devices configured to be charged when a predetermined voltage is applied and a second charging mode for charging other one of the external devices configured to be charged when a signal with a predetermined waveform is applied;
a charging module configured to charge one of the external devices connected to the information processor when the information processor is not in operation; and
a setting module configured to set, when an operating system is not in operation, one of the first charging mode and the second charging mode used by the executing module to the charging module so that the one of the first charging mode and the second charging mode is enabled when the information processor is not in operation, the one of the first charging mode and the second charging mode being capable of charging at least one of the external devices connected to the information processor.
5. An information processor comprising:
a storage module configured to store a plurality of charging modes capable of charging a plurality of external devices, respectively;
an input module configured to receive, when an operating system is not in operation, a selection request for selecting one of the charging modes;
an executing module configured to acquire, upon receipt of the selection request, one of the charging modes from the storage module, and to charge, when the operating system is not in operation, one of the external devices connected to the information processor by the one of the charging modes;
a charging module configured to charge, when the information processor is not in operation, one of the external devices connected to the information processor; and
a setting module configured to set the one of the charging modes used by the executing module to the charging module so that the one of the charging modes is enabled when the information processor is not in operation, wherein
the input module is further configured to receive a restart request for restarting the information processor and a save request for saving the one of the charging modes used by the executing module to charge the one of the external devices,
the storage module is configured to save the one of the charging modes in the save request when the input module receives the save request so that the saved one of the charging modes is enabled when the information processor is not in operation, and
the executing module is configured to stop charging the one of the external devices by the one of the charging modes when the input module receives the restart request while the operating system is not in operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method, comprising:
identifying a first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
2. A sub-system, comprising:
a component in communication with a plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one of the plurality of memory circuits that is not accessed by the system;
wherein the plurality of memory circuits is a rank.
3. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:
identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
4. The method of claim 3, wherein the power saving operation comprises:
a power down operation.
5. The method of claim 4, wherein the power down operation comprises:
a precharge power down operation.
6. The method of claim 3, wherein the at least one memory circuit has a clock enable input, the method further comprising:
initiating the power saving operation by utilizing the clock enable input of the at least one memory circuit.
7. The method of claim 6, wherein utilizing the clock enable input comprises:
de-asserting the clock enable input of the at least one memory circuit.
8. The method of claim 6, wherein the identifying comprises:
determining whether a page is being accessed in at least one of the plurality of memory circuits.
9. The method of claim 3, wherein the system further includes a component, and wherein:
at least one of the identifying and the initiating is carried out utilizing the component.
10. The method of claim 9, wherein the component includes an advanced memory buffer (AMB).
11. The method of claim 9, wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).
12. The method of claim 9, wherein the component includes a memory controller.
13. The method of claim 9, wherein the component includes a register.
14. The method of claim 3, wherein the memory includes a number (x) of the memory circuits, the method further comprising:
continuously subjecting a lesser number of the memory circuits to the power saving operation.
15. The method of claim 14, wherein the lesser number comprises x\u22121.
16. The method of claim 3, wherein the system further includes an interface circuit coupled to interface the plurality of memory circuits and the system, and wherein:
at least one of the identifying and the initiating is carried out utilizing the interface circuit.
17. The method of claim 3, wherein the memory circuits each includes dynamic random access memory (DRAM).
18. The method of claim 17, wherein the DRAM of each of the memory circuits each comprises a monolithic DRAM.
19. The method of claim 18, wherein the memory circuits are stacked.
20. The method of claim 18, wherein the memory circuits and the interface circuit are, stacked.
21. An apparatus for use with an electronic system, the apparatus comprising:
a first plurality of memory circuits; and
a component in communication with the first plurality of memory circuits and the system, the component operable to initiate a power savings operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank.
22. A method of operating a system, the system including a memory including \u201cx\u201d memory circuits, the method comprising:
accessing \u201cp\u201d of the memory circuits;
while the \u201cp\u201d memory circuits are being accessed, performing a power saving operation on \u201cq\u201d others of the memory circuits;
wherein \u201cp\u201d+\u201cq\u201d<=\u201cx\u201d;
wherein the \u201cx\u201d memory circuits is a rank.
23. The method of claim 22, wherein performing the power saving operation comprises:
de-asserting a clock enable input of the \u201cq\u201d memory circuits.
24. The method of claim 1, wherein initiating the power saving operation utilizes a clock enable input of the at least one memory circuit.
25. A method, comprising:
identifying one or more portions of at least one of a plurality of memory circuits that is not currently being accessed, the plurality of memory circuits being at least part of a rank; and
in response to the identification of the one or more portions of the at least one memory circuit, initiating a power saving operation in association with the one or more portions of the at least one memory circuit.
26. An apparatus comprising:
a first plurality of memory circuits; and
a component in communication with the first plurality of memory circuits and a system, the component operable to initiate a power saving operation in association with at least one memory circuit of a second plurality of memory circuits that is not accessed by the system, the first plurality of memory circuits including the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank;
wherein the component includes a circuit that is positioned on a dual in-line memory module (DIMM).
27. A method of managing power in an electronic system including a memory, the memory including a first plurality of memory circuits, the method comprising:
identifying the first plurality of memory circuits comprising at least one memory circuit of a second plurality of memory circuits that is not currently being accessed; and
in response to the identification of the at least one memory circuit, initiating a power saving operation in association with the at least one memory circuit of the second plurality of memory circuits;
wherein the first plurality of memory circuits is a rank;
wherein the system further includes a component, and at least one of the identifying and the initiating is carried out utilizing the component;
wherein the component includes a register.