1. A method for on-board programming andor In-System Configuration of a flash memory on a circuit board, comprising:
controlling inputs of the flash memory with an ASIC mounted on the circuit board via individual memory cells of a Boundary Scan register for activation or deactivation of a write operation, wherein
an architecture description of the ASIC and the flash memory to be programmed and the data format of the program and configuration data are provided in a file,
the printed circuit board is configured to be controlled via an interface for input or output of standard bus signals and for input of the control signals of the ASIC, and
the data of the network list or the circuit diagram which define the configuration of the interface between the flash memory to be programmed and the ASIC is provided in additional files.
2. The method according to claim 1, wherein the ASIC and flash memory to be programmed are controlled as a continuous unit.
3. The method according to claim 2, wherein a programming algorithm for programming the flash memory is created automatically by access to the additional file.
4. The method according to claim 1, further comprising simultaneously programming of a number of flash memories on the circuit board via the interface.
5. The method according to claim 1, further comprising providing a data register for buffering the address and control data occurring during burst mode operation, which is connected to the outputs of the ASIC provided for programming the flash memory.
6. A parallel interface for on-board programming andor In-System Configuration of a flash memory on a printed circuit board by controlling individual inputs of the flash memory with an ASIC mounted on the printed circuit board via memory cells of a Boundary Scan register for activating or deactivating a write operation, wherein the parallel interface is formed by a series connection of a number of memory cells which are part of the Boundary Scan register.
7. A parallel interface for on-board programming andor In-System Configuration of a flash memory on a printed circuit board by controlling individual inputs of the flash memory with an ASIC mounted on the printed circuit board via memory cells of a Boundary Scan register for activating or deactivating a write operation, wherein the parallel interface is formed by series connection of a number of memory cells of a data register used for In-System Configuration of the flash memory to be programmed.
8. A memory cell of a Boundary Scan register for on-board programming of a flash memory on a printed circuit board by controlling individual inputs of the flash memory with an ASIC mounted on the printed circuit board or activating or deactivating a write operation, comprising:
an input multiplexer for through connecting one of at least two input signals depending on a control signal present at a control signal input, which optionally switches through a connection from the ASIC or from a signal input for Boundary Scan test data to the flash memory;
a scan or capture flip-flop to buffer the programming data or the Boundary Scan test data received from the ASIC;
an update flip-flop for controlling individual control signal, data andor address inputs of the flash memory to initiate or end a write operation; and
an output multiplexer for through connecting one of at least two input signals, depending on a control signal present at a control signal input, which optionally switches through a connection from ASIC or from a signal input for configuration data to flash memory.
9. A memory cell of a data register for In-System Configuration of a flash memory on a printed circuit board by controlling individual inputs of the flash memory with an ASIC mounted on the printed circuit board for activating or deactivating a write operation, comprising:
a scan or capture flip-flop for buffering the configuration data received by the ASIC; and
an output multiplexer for through connecting one of two input signals, depending on a control signal present at a control signal input, which optionally switches through a connection from the ASIC or from a signal input for Boundary Scan test data or from a signal input from configuration data to the flash memory.
10. The memory cell according to claim 9, wherein instead of the output multiplexer an update flip-flop is used for controlling individual control signal, data andor address inputs of the flash memory in order to trigger or end a write operation.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A torsional vibration damper, comprising the following features:
a primary part with two lateral disks (1) and (2) which are connected with each other in a torsion-proof manner;
a secondary part with a middle disk (3) which is arranged between the lateral disks (1) and (2);
the primary part and the secondary part are in rotational connection with each other via springs (5);
damping chambers which are filled with a damping medium and respectively comprise at least one throttling opening;
guide elements (7.1) are provided for supporting and guiding the springs (5);
two guide elements (7.1) are associated with each spring (5), said guide elements being arranged at a mutual axial distance from each other and forming the support surfaces against a movement of the spring (5) in the radial and also axial direction characterized by the following features:
the guide elements (7.1) are connected with the lateral disks (1) and (2) in an entrainment-proof manner.
2. A torsional vibration damper according to claim 1, characterized in that the springs (5) are bow springs.
3. A torsional vibration damper according to claim 1, characterized by the following features:
each guide element (7.1) comprises at each end a stop cheek (7.2) for supporting the spring (5) or a spring assembly with inner springs arranged within an outer spring on the lateral disks (1, 2) during twisting between primary and secondary part.
4. A torsional vibration damper according to claim 3, characterized in that the guide element (7.1) and the stop cheeks (7.2) and (7.2) are integral.
5. A torsional vibration damper according to claim 4, characterized in that the guide element (7.1) and the stop cheeks (7.2) and (7.2) are produced in one single operation.
6. A torsional vibration damper according to claim 3, characterized in that at least one of the elements of guide element (7.1) and stop cheeks (7.2) and (7.2) consists of steel sheet.
7. A torsional vibration damper according to claim 2, characterized in that at least one of the elements of guide element (7.1) and stop cheeks (7.2) and (7.2) is massive.
8. A torsional vibration damper according to claim 1, characterized in that the lateral disks (1) and (2) comprise stop surfaces (1.1, 2.1) which cooperate with the stop cheeks (7.2) and (7.2).
9. A torsional vibration damper according to claim 1, characterized in that separate components are provided as stop cheeks, which are arranged either massively or as an injection-molded part or as a deep-drawn component.
10. A torsional vibration damper according to claim 1, characterized in that the lateral disks (1, 2) are provided with areas which are used as stop cheeks.
11. A torsional vibration damper according to claim 1, characterized in that the stop cheeks are respectively arranged as a separate component which is especially massive, or as an injection-molded part or as a deep-drawn component.
12. A torsional vibration damper according to claim 1, characterized in that the guide elements (7.1) are used for radially inner support andor sealing of a damping chamber.
13. A torsional vibration damper according to claim 1, characterized in that the two guide elements (7.1, 7.1), as seen in an axial sectional view through the rotational axis of the torsional vibration damper, have such a mutual axial distance from each other that the middle disk (3) can be guided radially to the outside between the two guide elements (7.1, 7.1).
14. A torsional vibration damper according to claim 1, characterized in that the damping chambers are arranged in a segment-like manner over the external circumference of the torsional vibration damper, and the springs (5) are positioned radially within the damping chambers, especially radially within the radially inner boundary surface of the damping chamber wall (6).
15. A torsional vibration damper according to claim 1, characterized in that a housing (4) is provided which encloses the primary part and the secondary part at least in part, with the housing (4), the primary part and the secondary part forming a modular unit.
16. A torsional vibration damper according to claim 1, characterized in that the guide element (7.1) comprises a plurality of passage openings (7.3) for guiding through damping medium or lubricating grease, said openings being especially arranged as through-holes.
17. A torsional vibration damper according to claim 6, characterized in that the lateral disks are provided with areas which are used as stop cheeks.
18. A torsional vibration damper according to claim 6, characterized in that the stop cheeks are respectively arranged as a separate component which is especially massive, or as an injection-molded part or as a deep-drawn component.