1. A non-volatile memory device, comprising
a semiconductor fin on an insulating layer;
a channel region at a central portion of the semiconductor fin;
sourcedrain regions on both sides of the semiconductor fin;
a floating gate arranged at a first side of the semiconductor fin and extending in a direction further away from the semiconductor fin; and
a first control gate arranged on top of the floating gate or covering top and sidewall portions of the floating gate.
2. The non-volatile memory device according to claim 1, wherein the semiconductor fin is a silicon fin.
3. The non-volatile memory device according to claim 1, wherein the floating gate comprises a floating gate dielectric layer and a floating gate conductor, and the floating gate conductor is insulated from the semiconductor fin by the floating gate dielectric layer.
4. The non-volatile memory device according to claim 3, wherein the floating gate conductor is a stack of a barrier layer and an floating gate conductive layer, and the barrier layer is sandwiched between the floating gate conductive layer and the floating gate dielectric layer.
5. The non-volatile memory device according to claim 1, wherein the first control gate comprises an intermediate dielectric layer and a first control gate conductor.
6. The non-volatile memory device according to claim 5, wherein the first control gate conductor is made of at least one selected from a group comprising metals, doped polysilicon, and conductive nitride.
7. The non-volatile memory device according to claim 6, wherein the first control gate conductor is a stack of a barrier layer and an control gate conductive layer, and the barrier layer is sandwiched between the control gate conductive layer and the intermediate dielectric layer.
8. The non-volatile memory device according to claim 1, wherein the insulating layer is a buried insulating layer of an SOI wafer.
9. The non-volatile memory device according to claim 8, wherein the semiconductor fin is formed by a top semiconductor layer of the SOI wafer.
10. The non-volatile memory device according to any one of claims 1-9, further comprising:
a second control gate arranged at a second side opposite to the first side of the semiconductor fin and extending in a direction further away from the semiconductor fin.
11. The non-volatile memory device according to claim 10, wherein the second control gate and the floating gate are made of the same dielectric material and conductive material.
12. A method for manufacturing a non-volatile memory device, comprising:
a) forming a semiconductor fin on an insulating layer;
b) forming a floating gate on a first side of the semiconductor fin, the floating gate extending in a direction further away form the semiconductor fin;
c) forming sourcedrain region on both sides of the semiconductor fin; and
d) forming a first control gate on top of the floating gate or on top and sidewall portions of the floating gate.
13. The method according to claim 12, wherein the insulating layer is a buried insulating layer on an SOI wafer, and the step a) comprises:
a1) forming a first oxide layer on the SOI wafer;
a2) forming a first nitride layer on the first oxide layer; and
a3) patterning the first nitride layer, the first oxide layer, and a top semiconductor layer of the SOI wafer with a mask, to provide a semiconductor fin in a stripe covered with the first nitride layer and the first oxide layer thereon.
14. The method according to claim 12, wherein the step b) comprises:
b1) forming a floating gate dielectric layer on the whole surface;
b2) forming a barrier layer on the floating gate dielectric layer;
b3) forming a floating gate conductive layer on the whole surface;
b4) planarizing the floating gate conductive layer to remove the portions of the floating gate conductive layer, the barrier layer and the floating gate dielectric layer above the semiconductor fin; and
b5) patterning the floating gate conductive layer and the barrier layer into a stripe extending in a direction substantially perpendicular to the direction along which the semiconductor fin extends.
15. The method according to claim 12, wherein the step d) comprises:
d1) forming a second nitride layer on the floating gate;
d2) forming a second oxide layer on the second nitride layer;
d3) forming an opening in the second nitride layer and the second oxide layer either to expose a top portion of the floating gate, or to expose top and sidewall portions of the floating gate;
d4) forming an intermediate dielectric layer at least on inner walls of the opening; and
d5) filling the opening with a conductive material to provide a first control gate conductor.
16. The method according to any one of claims 12-15, wherein in step b), the second control gate is formed simultaneously with the floating gate, and the second control gate is arranged at a second side opposite to the first side of the semiconductor fin, and extends in a direction further away from the semiconductor fin.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of tuning a dielectric resonator which resonator comprises a cavity within which is mounted a dielectric which method comprises changing the frequency of the resonator by a frequency changing means which is operated using a ferroelectric element in which a DC bias is applied across the ferroelectric element to decrease the relative permittivity of the ferroelectric element which affects the dielectric resonator electric field and changes the resonance frequency of the resonator, in which the ferroelectric element is a ferroelectric film, in which the ferroelectric film is mounted on a conductive base on which is positioned a spacer and the dielectric is mounted on the spacer, in which the conductive base, on which is formed the ferroelectric element, is supported on a floor of the resonator, the dielectric element and spacer are ring shaped, the spacer is positioned on the ferroelectric element and the dielectric element is placed on the spacer, and in which there is a wire electrode which passes through the spacer and the dielectric element and is connected to the ferroelectric element, there being a means to apply a DC bias to the ferroelectric element through the conductive base and the wire.
2. A method as claimed in claim 1 in which the spacer is made of a low loss low dielectric constant spacer.
3. A method as claimed in claim 1 in which the ferroelectric element is ferroelectric film grown on a conductive substrate.
4. A method as claimed in claim 1 in which the ferroelectric element is ferroelectric film grown on a resonator cavity bottom, a resonator upper plate, or on one or more of resonator surrounding cavity walls.
5. A tuneable dielectric resonator which comprises a cavity within which is mounted a dielectric and a frequency changing means and in which the frequency changing means is operated using a ferroelectric element, in which a DC bias is applied across the ferroelectric element to decrease the relative permittivity of the ferroelectric element which affects the dielectric resonator electric field and changes the resonance frequency of the resonator, in which the ferroelectric element is a ferroelectric film, in which the ferroelectric film is mounted on a conductive base on which is positioned a spacer and the dielectric is mounted on the spacer, in which the conductive base, on which is formed the ferroelectric element, is supported on a floor of the resonator, the dielectric element and spacer are ring shaped, the spacer is positioned on the ferroelectric element and the dielectric element is placed on the spacer, and in which there is a wire electrode which passes through the spacer and the dielectric element and is connected to the ferroelectric element, there being a means to apply a DC bias to the ferroelectric element through the conductive base and the wire.
6. A tuneable dielectric resonator as claimed in claim 5 in which the spacer is made of a low loss low dielectric constant.
7. A tuneable dielectric resonator as claimed in claim 5 in which the ferroelectric element is mounted on the resonator cavity bottom or resonator upper plate, or surrounding resonator cavity walls.
8. A tuneable dielectric resonator as claimed in claim 5 in which the frequency changing means comprises a ferroelectric element on which is mounted a dielectric resonator.
9. A tuneable dielectric resonator as claimed in claim 5 in which the ferroelectric material is BaxSr1-xTiO3.