1. A method for reducing static power consumption of a processor, comprising:
comparing a cost of entering into and recovering from a nap mode with the cost of not entering the nap mode;
if the cost of entering into and recovering from the nap mode is less than the cost of not entering the nap mode,
halting an instruction-processing portion of the processor, and
reducing a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor;
whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
2. The method of claim 1, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
3. The method of claim 1, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
4. The method of claim 3, further comprising saving state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
5. The method of claim 4, wherein upon receiving a wakeup signal the method further comprises:
restoring full voltage to the instruction-processing portion of the processor;
restoring state information to the instruction-processing portion of the processor; and
resuming processing of computer instructions.
6. The method of claim 1, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
7. The method of claim 1, further comprising reducing the voltage to a cache memory portion of the processor upon receiving the signal.
8. The method of claim 7, further comprising writing cache memory data to main memory prior to reducing the voltage.
9. The method of claim 1, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
10. The method of claim 1, wherein the second portion of the processor includes a cache memory portion of the processor.
11. An apparatus, for reducing static power consumption of a processor, comprising:
a comparison mechanism that is configured to compare a cost of entering into and recovering from a nap mode with the cost of not entering the nap mode;
a halting mechanism that is configured to halt an instruction-processing portion of the processor; and
a voltage reducing mechanism that is configured to reduce a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor;
wherein if the cost of entering into and recovering from the nap mode is less than the cost of not entering the nap mode the halting mechanism is configured to halt an instruction-processing portion of the processor and the voltage-reducing mechanism is configured to reduce the voltage supplied to the instruction-processing portion of the processor;
whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
12. The apparatus of claim 11, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a minimum value that maintains state information within the instruction-processing portion of the processor.
13. The apparatus of claim 11, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to zero.
14. The apparatus of claim 13, further comprising a saving mechanism that is configured to save state information from the instruction-processing portion of the processor prior to reducing the voltage supplied to the instruction-processing portion of the processor, wherein saving state information includes saving state information to one of, the second portion of the processor and a main memory.
15. The apparatus of claim 14, further comprising:
a voltage restoring mechanism that is configured to restore full voltage to the instruction-processing portion of the processor;
a state restoring mechanism that is configured to restore state information to the instruction-processing portion of the processor; and
a resuming mechanism that is configured to resume processing of computer instructions.
16. The apparatus of claim 11, wherein maintaining full voltage to the second portion of the processor involves maintaining full voltage to a snoop-logic portion of the processor, whereby the processor can continue to perform cache snooping operations while the instruction-processing portion of the processor is in the reduced power mode.
17. The apparatus of claim 11, wherein the voltage reducing mechanism is further configured to reduce the voltage to a cache memory portion of the processor upon receiving the signal.
18. The apparatus of claim 17, further comprising a writing mechanism that is configured to write cache memory data to main memory prior to reducing the voltage.
19. The apparatus of claim 11, wherein the second portion of the processor includes a control portion of the processor that includes interrupt and clock circuitry.
20. (canceled)
21. A method for reducing static power consumption of a processor, comprising:
receiving a signal indicating that instruction execution within the processor is to be temporarily halted; and
in response to the signal,
halting an instruction-processing portion of the processor, and
reducing a voltage supplied to the instruction-processing portion of the processor, while maintaining full voltage to a second portion of the processor, wherein reducing the voltage supplied to the instruction-processing portion of the processor involves reducing the voltage to a value that will maintain state information within the instruction-processing portion of the processor but which is not sufficient to allow processing to continue;
whereby the second portion of the processor can continue to operate while the instruction-processing portion of the processor is in a reduced power mode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A seed of hybrid maize variety X8H565, produced by crossing a first plant of variety PH12 KP with a second plant of variety PHVRZ, wherein representative seed of said varieties PH12 KP and PHVRZ have been deposited under ATCC Accession Number PTA-12653 and PTA-11865, respectively.
2. A plant or plant part produced by growing the seed of the hybrid maize variety of claim 1.
3. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 2, and wherein application of said techniques results in the production of said second maize plant.
4. The method of claim 3, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation; and
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce an inbred maize plant derived from hybrid maize variety X8H565.
5. The method of claim 3, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce an inbred maize plant derived from hybrid maize variety X8H565.
6. A seed of hybrid maize variety X8H565 further comprising a locus conversion, wherein said seed is produced by crossing a first plant of variety PH12 KP with a second plant of variety PHVRZ; wherein representative seed of said varieties PH12 KP and PHVRZ have been deposited under ATCC Accession Number PTA-12653 and PTA-11865, respectively; and wherein at least one of said varieties PH12 KP and PHVRZ further comprises a locus conversion.
7. The seed of claim 6, wherein the locus conversion confers a trait selected from the group consisting of male sterility, site-specific recombination, abiotic stress tolerance, altered phosphorus, altered antioxidants, altered fatty acids, altered essential amino acids, altered carbohydrates, herbicide tolerance, insect resistance and disease resistance.
8. A plant or plant part produced by growing the seed of the maize hybrid variety of claim 6.
9. A method for producing a second maize plant comprising applying plant breeding techniques to a first maize plant, or parts thereof, wherein said first maize plant is the maize plant of claim 8, and wherein application of said techniques results in the production of said second maize plant.
10. The method of claim 9, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with itself or another maize plant to produce seed of a subsequent generation;
(b) harvesting and planting the seed of the subsequent generation to produce at least one plant of the subsequent generation; and
(c) repeating steps (a) and (b) for an additional 2-10 generations to produce an inbred maize plant derived from hybrid maize variety X8H565.
11. The method of claim 9, further defined as producing an inbred maize plant derived from hybrid maize variety X8H565, the method comprising the steps of:
(a) crossing said first maize plant with an inducer variety to produce haploid seed; and
(b) doubling the haploid seed to produce an inbred maize plant derived from hybrid maize variety X8H565.