1. A method of programming a phase change memory device, the method comprising:
programming write data in a plurality of phase change memory cells by applying write pulses to each of the plurality of phase change memory cells; and
verifying whether each of the phase change memory cells is programmed by applying at least one verification pulse to each of the phase-change memory cells, wherein a number of applications for the at least one verification pulse and corresponding intervals between applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.
2. The method of claim 1, wherein the at least one verification pulse is not applied to a first phase change memory cell when the first phase change memory cell passes verification.
3. The method of claim 1, wherein the at least one verification pulse is continuously applied to a second phase change memory cell until the second phase change memory cell passes verification within a defined number of applications for the at least one verification pulse.
4. The method of claim 3, wherein the at least one verification pulse is applied to each of the phase-change memory cells at regular intervals.
5. The method of claim 3, wherein the at least one verification pulse is applied to each of the phase-change memory cells at increasing intervals.
6. The method of claim 3, wherein the second phase change memory cell is determined to fail verification when the second phase change memory cell does not pass verification within the defined number of applications for the at least one verification pulse.
7. The method of claim 6, wherein the write pulses and the at least one verification pulse are repeatedly applied to the second phase change memory cell which is determined to fail verification.
8. The method of claim 1, wherein verifying whether each of the phase change memory cells is programmed is simultaneously performed on a plurality of groups, each group including the phase change memory cells.
9. A phase change memory device, comprising:
a memory cell array including a plurality of phase change memory cells;
an inputout (IO) circuit, connected to each of the phase change memory cells through each of plurality of bit line selection transistors and configured to perform a program operation, a verification operation and a read operation on the phase change memory cells; and
a control circuit configured to control the IO circuit such that write data is programmed in the phase change memory cells by applying write pulses to each of the phase change memory cells, such that a determination of whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells, wherein a number of applications of the at least one verification pulse and corresponding intervals between applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.
10. The phase change memory device of claim 9, wherein the IO circuit comprises:
a write driver configured to write data in the each the phase change memory cells by providing the write pulses to each of the phase change memory cells in response to a first control signal; and
a sensing unit configured to provide the at least one verification pulse to each of the phase-change memory cells in response to a second control signal, to sense data written in each of the phase-change memory cells in response to a third control signal and to compare the sensed data with the write data to provide a comparison signal.
11. The phase change memory device of claim 10, wherein the sensing unit comprises:
a precharging unit configured to apply the at least one verification pulse to the phase change memory cell;
a sense amplifier configured to sense the data written in the phase change memory cell; and
a comparator configured to compare the sensed data with the write data to provide the comparison signal.
12. The phase change memory device of claim 10, wherein the sensing unit comprises:
a precharging unit configured to apply the at least one verification pulse to the phase change memory cell; and
a sense amplifier configured to compare the data written in the phase change memory cell with a reference voltage to provide the comparison signal.
13. The phase change memory device of claim 10, wherein the control circuit comprises:
a control voltage generating unit configured to generate first and second control voltages for generating the write pulses and the at least one verification pulse;
a counter configured to count the comparison signal from the sensing unit to provide an output signal;
a delay unit configured to generate a delay control signal for controlling an applying time of the at least one verification pulse, in response to the output signal; and
a state circuit configured to receive the comparison signal and the output signal to output a state signal representing whether each of the phase change memory cells is programmed.
14. The phase change memory device of claim 13, wherein the control circuit controls the state circuit such that the state signal represents a pass when the comparison signal represents a program pass.
15. The phase change memory device of claim 13, wherein the control circuit controls the state circuit such that the state signal represents a fail, when the comparison signal does not represents a program pass within a predetermined value.
16. The phase change memory device of claim 10, further comprising:
an IO buffer configured to temporarily store the write data, wherein the control circuit controls the IO buffer and the IO circuit, such that the verification operation is simultaneously performed across a plurality of groups, each group including the phase change memory cells.
17. A memory system comprising:
a phase change memory device including a plurality of phase change memory cells storing data; and a memory controller configured to control the phase change memory device,
wherein the phase change memory device comprises:
an inputout (IO) circuit, connected to each of the phase change memory cells through each of plurality of bit line selection transistors and configured to perform a program operation, a verification operation and a read operation on the phase change memory cells; and
a control circuit configured to control the IO circuit such that write data is programmed in the phase change memory cells by applying write pulses to each of the phase change memory cells, such that a determination of whether each of the phase change memory cells is programmed is verified by applying at least one verification pulse to each of the phase-change memory cells, wherein a number of applications of the at least one verification pulse and corresponding intervals between applications of the at least one verification pulse are varied in accordance with a verification result for each of the phase-change memory cells.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A fuel cell system comprising:
a fuel cell for generating electricity by chemical reaction between fuel gas and oxidant gas;
a supply channel for flowing said fuel gas supplied from fuel supply device to said fuel cell;
a circulation channel which is connected to said supply channel and which is for circulating exhaust gas, discharged from a fuel electrode of said fuel cell, to said fuel cell; and
an exhaust gas recovery channel which divides from said circulation channel and is connected to said circulation channel or said supply channel,
wherein said exhaust gas recovery channel comprises
a first control valve controlled by a control device,
a first exhaust gas storage unit connected to said first control valve, and
a pressure adjusting unit for setting said first exhaust gas storage unit to a negative pressure.
2. A fuel cell system according to claim 1, wherein said circulation channel includes a gas-liquid separating device for separating water and gas from the exhaust gas.
3. A fuel cell system according to claim 1, wherein said exhaust gas recovery channel includes a second exhaust gas storage unit, and a second control valve provided at a connection portion of said exhaust gas recovery channel and said supply channel, in addition to said first exhaust gas storage unit,
and wherein said pressure adjusting unit sets said first exhaust gas storage unit to a negative pressure and also pressurizes said second exhaust gas storage unit,
and wherein said control device controls opening of said first control valve and said second control valve.
4. A fuel cell system according to claims 1, wherein said exhaust gas recovery channel includes a fuel gas separating device for selectively separating fuel gas from the exhaust gas.
5. A fuel cell system according to claim 4, wherein reactant gas included in impurity gas yielded by separating the fuel gas from the exhaust gas by said fuel gas separating device is burnt by a combustion device connected to said fuel gas separating device.
6. A fuel cell system according to claims 1, wherein said exhaust gas recovery channel further comprises a bypass channel circumventing said pressure adjusting unit,
and wherein said bypass channel includes a check valve for restricting backflow of the exhaust gas.