1461148065-da284243-ecd1-4f97-838b-015f5e33753e

What is claimed is:

1. A method of stitching three resistive layers in a MONOS memory array to three conductive layers comprising:
providing a MONOS memory array having said three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; and
periodically contacting each of said resistive layers by a respective upper conductive layer wherein said contacting is said stitching wherein said contacting comprises:
periodically connecting said middle resistive layer to a bottom conductive layer overlying said top resistive layer;
cutting said middle resistive layer to expose said bottom resistive layer;
building a contactvia stack from said exposed bottom resistive layer to a top conductive layer;
connecting cut ends of said middle resistive layer by contacting said ends of said middle resistive layer to a middle conductive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contactvia stack; and
connecting said top resistive layer to said middle conductive layer.
2. The method according to claim 1 wherein said stitching is done on alternate sets of resistive lines.
3. The method according to claim 1 wherein said bottom and middle resistive lines are a bit line and a control gate line and wherein said top resistive line is a word gate line.
4. The method according to claim 1 wherein said bottom and middle resistive lines are a word line and a control gate line and wherein said top resistive line is a bit line.
5. The method according to claim 1 wherein said stitching method reduces resistance of said MONOS memory array.
6. The method according to claim 1 wherein said stitching method is performed within a cell size limited by a minimum metal pitch.
7. A method of stitching three resistive layers in a MONOS memory array to three conductive layers comprising:
providing a MONOS memory array having said three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; and
periodically contacting each of said resistive layers by a respective upper conductive layer wherein said contacting is said stitching wherein said contacting comprises:
periodically connecting said top resistive layer to a bottom conductive layer overlying said top resistive layer;
cutting said middle resistive layer to expose said bottom resistive layer;
building a contactvia stack from said exposed bottom resistive layer to a top conductive layer;
connecting cut ends of said middle resistive layer by contacting said ends of said middle resistive layer to said bottom conductive layer wherein said bottom conductive layer loops around said contactvia stack; and
connecting said middle resistive layer to a middle conductive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer.
8. The method according to claim 7 wherein said stitching is done on alternate sets of resistive lines.
9. The method according to claim 7 wherein said bottom and middle resistive lines are a bit line and a control gate line and wherein said top resistive line is a word gate line.
10. The method according to claim 7 wherein said bottom and middle resistive lines are a word line and a control gate line and wherein said top resistive line is a bit line.
11. The method according to claim 7 wherein said stitching method reduces resistance of said MONOS memory array.
12. The method according to claim 7 wherein said stitching method is performed within a cell size limited by a minimum metal pitch.
13. A method of stitching resistive layers in a MONOS memory array comprising:
providing a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said bit diffusion junctions run in parallel and wherein said word gates run orthogonally to said control gates and said bit diffusion junctions;

wherein word gates in said array from word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
periodically connecting said control gate lines to a middle conductive layer overlying said word gate lines;
cutting said control gate lines to expose said bit lines;
building a contactvia stack from said exposed bit lines to a top conductive layer wherein said top conductive layer overlies said middle conductive layer;
connecting cut ends of said control gate lines by contacting said ends of said control gate lines to a bottom conductive layer wherein said bottom conductive layer underlies said middle conductive layer and wherein said bottom conductive layer loops around said contactvia stack; and
connecting said word gate lines to said bottom conductive layer.
18. The method according to claim 17 wherein said stitching is done on alternate sets of control gate lines and bit lines.
19. The method according to claim 17 wherein said stitching method reduces resistance of said MONOS memory array.
20. The method according to claim 17 wherein said stitching method is performed within a cell size limited by a minimum metal pitch.
21. A method of stitching resistive layers in a MONOS memory array comprising:
providing a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said bit diffusion junctions run in parallel and wherein said word gates run orthogonally to said control gates and said bit diffusion junctions;

wherein word gates in said array from word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
periodically contacting each of said word lines, control gate lines, and bit lines by a respective upper conductive layer wherein said contacting is said stitching wherein said contacting comprises:
periodically connecting said control gate lines to a middle conductive layer overlying said word gate lines;
cutting said control gate lines to expose said bit lines; building a contactvia stack from said exposed bit lines to a top conductive layer wherein said top conductive layer overlies said middle conductive layer;
connecting cut ends of said control gate lines by contacting said ends of said control gate lines to a bottom conductive layer wherein said bottom conductive layer underlies said middle conductive layer and wherein said bottom conductive layer loops around said contactvia stack; and
connecting said word gate lines to said bottom conductive layer.; and

adding select transistors into areas of said stitching between sub-arrays of said MONOS memory cells.
22. The method according to claim 21 wherein said stitching is done on alternate sets of control gate lines and bit lines.
23. The method according to claim 21 wherein said stitching method reduces resistance of said MONOS memory array.
24. The method according to claim 21 wherein said stitching method is performed within a cell size limited by a minimum metal pitch.
25. The method according to claim 21 wherein said step of adding select transistors into areas of said stitching between sub-arrays of said MONOS memory cells comprises:
extending alternate said bit diffusions past an edge of said control gates prior to formation of said control gates; and
forming bit line select transistors alternately with said extended bit diffusions on either side of each of said sub-arrays and horizontally across said extended bit diffusions; and
connecting unextended bit diffusions to said bit lines by contact stacks to said middle conductive layer.
26. The method according to claim 21 wherein said step of adding select transistors into areas of said stitching between sub-arrays of said MONOS memory cells comprises:
forming pairs of control gate select transistors between said sub-arrays; and
forming control gate contacts over shallow trench isolation areas wherein center control gate contacts lie between two control gate select transistors of a pair and wherein outer control gate contacts lie on outer sides of each of said pairs, wherein said center control gate contacts are connected to said control gate lines by said top conductive lines and wherein said outer control gates contact control gates of a nearest said sub-array.
27. The method according to claim 1 wherein each of said sub-array control gates is connected by said bottom conductive layer to a source diffusion of said control gate select transistor.
28. The method according to claim 21 wherein each of said sub-array control gates is extended to a source diffusion of a corresponding said control gate select transistor thereby directly connecting each of said control gates to a corresponding control gate select transistor source diffusion.
29. The method according to claim 26 wherein said control gate select transistors are chosen from the group consisting of: an N-channel device in an isolated P-well, and a P-channel device in an independent N-well.
30. The method according to claim 26 wherein said pairs of control gate select transistors run in parallel with said word lines and perpendicular to said bit lines and said control gate lines.
31. The method according to claim 21 wherein said step of adding select transistors into areas of said stitching between sub-arrays of said MONOS memory cells comprises:
extending alternate said bit diffusions past an edge of said control gates prior to formation of said control gates;
forming bit line select transistors alternately with said extended bit diffusions on either side of each of said sub-arrays and horizontally across said extended bit diffusions;
connecting unextended bit diffusions to said bit lines by contact stacks to said middle conductive layer;
forming pairs of control gate select transistors out of phase with and between two of said bit line select transistors inside two edges of two said sub-arrays; and
forming control gate contacts over shallow trench isolation areas wherein center control gate contacts lie between two control gate select transistors of a pair and wherein outer control gate contacts lie on outer sides of each of said pairs, wherein said center control gate contacts are connected to said control gate lines by said top conductive layer and wherein said outer control gates contact control gates of a nearest said sub-array.
32. The method according to claim 31 wherein each of said sub-array control gates is connected by one of said bottom conductive layer to a source diffusion of said control gate select transistor.
33. The method according to claim 31 wherein each of said sub-array control gates is extended to a source diffusion of a corresponding said control gate select transistor thereby directly connecting each of said control gates to a corresponding control gate select transistor source diffusion.
34. The method according to claim 31 wherein said control gate select transistors are chosen from the group consisting of: an N-channel device in an isolated P-well, and a P-channel device in an independent N-well.
35. The method according to claim 31 wherein said pairs of control gate select transistors run in parallel with said word lines and perpendicular to said bit lines and said control gate lines.
36. A method of stitching resistive layers in a MONOS memory array comprising:
providing a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said word gates run in parallel and wherein said bit diffusion junctions run orthogonally to said control gates and said word gates;

wherein word gates in said array form word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
periodically connecting said bit lines to a bottom conductive layer overlying said word gate lines;
periodically connecting said control gate lines to a middle conductive layer;
building a contactvia stack from said word gate lines to a top conductive layer overlying said middle conductive layer; and
contacting said control gate lines to a bottom conductive layer wherein said bottom conductive layer underlies said middle conductive layer and loops around said contactvia stack.
37. The method according to claim 36 wherein said stitching is done on alternate sets of control gate lines and word lines.
38. The method according to claim 36 wherein said middle conductive line and said top conductive line are shifted by half a metal pitch, wherein said middle conductive layer also loops around said contactvia stack, and wherein said stitching is done on every control gate line and on alternate sets of word lines.
39. The method according to claim 36 wherein said stitching method reduces resistance of said MONOS memory array.
40. The method according to claim 36 wherein said stitching method is performed within a cell size limited by a minimum metal pitch.
41. A stitched MONOS memory array comprising:
three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; and
stitches periodically contacting each of said resistive layers to a respective upper conductive layer wherein said stitches comprise:
connections from said middle resistive layer to a bottom conductive layer overlying said top resistive layer;
contactvia stacks from said bottom resistive layer to a top conductive layer;
a middle conductive layer connecting cut ends of said middle resistive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contactvia stacks; and
connections from said top resistive layer to said middle conductive layer.
42. The memory array according to claim 41 wherein said stitches are located on alternate sets of resistive lines.
43. The memory array according to claim 41 wherein said bottom and middle resistive lines are a bit line and a control gate line and wherein said top resistive line is a word gate line.
44. The memory array according to claim 41 wherein said bottom and middle resistive lines are a word line and a control gate line and wherein said top resistive line is a bit line.
45. The memory array according to claim 41 wherein said stitches reduce resistance of said MONOS memory array.
46. The memory array according to claim 41 wherein said stitches lie within a cell size limited by a minimum metal pitch.
47. A stitched MONOS memory array comprising:
three resistive layers wherein said three resistive layers are vertically stacked as a bottom, middle, and top resistive layer and wherein said bottom and middle resistive layers run in parallel to each other and wherein said top resistive layer runs orthogonally to said bottom and middle resistive layers; and
stitches periodically contacting each of said resistive layers by a respective upper conductive layer wherein said stitches comprise:
connections from said top resistive layer to a bottom conductive layer overlying said top resistive layer;
contactvia stacks from said bottom resistive layer to a top conductive layer;
a bottom conductive layer connecting cut ends of said middle resistive layer wherein said bottom conductive layer loops around said contactvia stacks; and
connections from said middle resistive layer to a middle conductive layer wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer.
48. The memory array according to claim 47 wherein said stitches lie on alternate sets of resistive lines.
49. The memory array according to claim 47 wherein said bottom and middle resistive lines are a bit line and a control gate line and wherein said top resistive line is a word gate line.
50. The memory array according to claim 47 wherein said bottom and middle resistive lines are a word line and a control gate line and wherein said top resistive line is a bit line.
51. The memory array according to claim 47 wherein said stitches reduce resistance of said MONOS memory array.
52. The memory array according to claim 47 wherein said stitches lie within a cell size limited by a minimum metal pitch.
53. A stitched MONOS memory array comprising:
a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said bit diffusion junctions run in parallel and wherein said word gates run orthogonally to said control gates and said bit diffusion junctions;

wherein word gates in said array form word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
connections from said control gate lines to a bottom conductive layer overlying said word gate lines;
contactvia stacks from said bit lines to a top conductive layer;
a middle conductive layer connecting cut ends of said control gate lines wherein said middle conductive layer overlies said bottom conductive layer and underlies said top conductive layer and wherein said middle conductive layer loops around said contactvia stacks; and
connections from said word gate lines to said middle conductive layer.
54. The memory array according to claim 53 wherein said connections lie on alternate sets of control gate lines, bit lines, and word lines.
55. A stitched MONOS memory array comprising:
a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said bit diffusion junctions run in parallel and wherein said word gates run orthogonally to said control gates and said bit diffusion junctions;

wherein word gates in said array from word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
connections from said control gate lines to a middle conductive layer overlying said word gate lines;
contactvia stacks from said bit lines to a top conductive layer wherein said top conductive layer overlies said middle conductive layer;
a bottom conductive layer connecting cut ends of said control gate lines wherein said bottom conductive layer underlies said middle conductive layer and wherein said bottom conductive layer loops around said contactvia stacks; and
connections from said word gate lines to said bottom conductive layer.
56. The memory array according to claim 55 wherein said connections lie on alternate sets of control gate lines and bit lines.
57. A stitched MONOS memory array comprising:
a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said bit diffusion junctions run in parallel and wherein said word gates run orthogonally to said control gates and said bit diffusion junctions;

wherein word gates in said array from word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
stitches periodically contacting each of said word lines, control gate lines, and bit lines by a respective upper conductive layer wherein said contacting comprises:
connections from said control gate lines to a middle conductive layer overlying said word gate lines;
contactvia stacks from said bit lines to a top conductive layer wherein said top conductive layer overlies said middle conductive layer;
a bottom conductive layer connecting cut ends of said control gate lines wherein said bottom conductive layer underlies said middle conductive layer and wherein said bottom conductive layer loops around said contactvia stacks; and
connections from said word gate lines to said bottom conductive layer.; and

select transistors in areas of said stitching between sub-arrays of said MONOS memory cells.
58. The memory array according to claim 57 wherein said stitches lie on alternate sets of control gate lines and bit lines.
59. The memory array according to claim 57 wherein said select transistors comprise:
extensions of alternate said bit diffusions past an edge of said control gates;
bit line select transistors placed alternately with said extended bit diffusions on either side of each of said sub-arrays and horizontally across said extended bit diffusions wherein unextended said bit diffusions are connected to said bit lines by contact stacks to said middle conductive layer.
60. The memory array according to claim 57 wherein said select transistors comprise:
pairs of control gate select transistors between said sub-arrays; and
control gate contacts over shallow trench isolation areas wherein center control gate contacts lie between two control gate select transistors of a pair and wherein outer control gate contacts lie on outer sides of each of said pairs, wherein said center control gate contacts are connected to said control gate lines by said top conductive layer and wherein said outer control gates contact control gates of a nearest said sub-array.
61. The memory array according to claim 60 wherein each of said sub-array control gates is connected by said bottom conductive layer to a source diffusion of said control gate select transistor.
62. The memory array according to claim 60 wherein each of said sub-array control gates is extended to a source diffusion of a corresponding said control gate select transistor thereby directly connecting each of said control gates to a corresponding control gate select transistor source diffusion.
63. The memory array according to claim 60 wherein said control gate select transistors are chosen from the group consisting of: an N-channel device in an isolated P-well, and a P-channel device in an independent N-well.
64. The memory array according to claim 60 wherein said pairs of control gate select transistors run in parallel with said word lines and perpendicular to said bit lines and said control gate lines.
65. The memory array according to claim 57 wherein said select transistors comprise:
extensions of alternate said bit diffusions past an edge of said control gates;
bit line select transistors placed alternately with said extended bit diffusions on either side of each of said sub-arrays and horizontally across said extended bit diffusions wherein unextended said bit diffusions are connected to said bit lines by contact stacks to said middle conductive layer;
pairs of control gate select transistors placed out of phase with and between two of said bit line select transistors inside two edges of two said sub-arrays; and
control gate contacts over shallow trench isolation areas wherein center control gate contacts lie between two control gate select transistors of a pair and wherein outer control gate contacts lie on outer sides of each of said pairs, wherein said center control gate contacts are connected to said control gate lines by said top conductive layer and wherein said outer control gates contact control gates of a nearest said sub-array.
66. The memory array according to claim 65 wherein each of said sub-array control gates is connected by said bottom conductive layer to a source diffusion of said control gate select transistor.
67. The memory array according to claim 65 wherein each of said sub-array control gates is extended to a source diffusion of a corresponding said control gate select transistor thereby directly connecting each of said control gates to a corresponding control gate select transistor source diffusion.
68. The memory array according to claim 65 wherein said control gate select transistors are chosen from the group consisting of: an N-channel device in an isolated P-well, and a P-channel device in an independent N-well.
69. The memory array according to claim 65 wherein said pairs of control gate select transistors run in parallel with said word lines and perpendicular to said bit lines and said control gate lines.
70. A stitched MONOS memory array comprising:
a plurality of memory cells in a MONOS memory array wherein each memory cell comprises:
a storage cell on either side of a word gate;
a bit diffusion junction underlying each of said storage cells wherein each of said bit diffusion junctions is shared with an adjacent storage cell of an adjacent memory cell; and
a control gate overlying each of said storage cells electrically isolated from underlying said bit diffusion junctions wherein said control gates and said word gates run in parallel and wherein said bit diffusion junctions run orthogonally to said control gates and said word gates;

wherein word gates in said array form word lines, said control gates in said array form control gate lines, and said bit diffusion junctions in said array form bit lines;
connections from said bit lines to a bottom conductive layer overlying said word gate lines;
connections from said control gate lines to a middle conductive layer;
contactvia stacks from said word gate lines to a top conductive layer overlying said middle conductive layer; and
a bottom conductive layer contacting said control gate lines wherein said bottom conductive layer underlies said middle conductive layer and loops around said contactvia stacks.
71. The memory array according to claim 70 wherein said connections lie on alternate sets of control gate lines and word lines.
72. The memory array according to claim 70 wherein said middle conductive line and said top conductive line are shifted by half a metal pitch, wherein said middle conductive layer also loops around said contactvia stack, and wherein said connections lie on every control gate line and on alternate sets of word lines.

The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.

1-18. (canceled)
19. An image processing device for a combat type game, the device being arranged i) to set up in virtual space a first model being controlled by a player and a second controlled model where the first model and the second model combat each other; and ii) to control the models such that they move in prescribed directions in the virtual space and cause a display means to display images of a virtual space from a virtual viewpoint, the device comprising:
means for image processing whereby execution of a prescribed motion operation by a player controlling the first model, while the game is in progress, causes a virtual attractive force to be set up to act between the first model and the second model and to cause the first model to automatically move around the second model being a center of the virtual attractive force.
20. The image processing device according to claim 19, wherein the image processing means is further operable so that an amount of frictional force that is applied to the models varies according to whether the models are moving or whether they are stationary.
21. The image processing device according to claim 19 or claim 20, wherein the image processing means is further operable so that a projection image of the models is displayed matching the surface shape of a stage on which the models are placed.
22. The image processing device according to claim 19 or claim 20, wherein the image processing means is further operable so that a determination is performed of an overlap of a field of view created by the virtual viewpoint with respect to the model that is the subject of display and another model which is not set as the subject of display, and, if the result of this determination is affirmative, the other model is not displayed.
23. The image processing device according to claim 19 or claim 20, wherein the image processing means is further operable so that, with respect to the end-point of a predetermined movement track of the model, a target point is set up different from the end-point and the movement track is interpolated such that the end-point coincides with the target point.
24. The image processing device according to claim 19 or claim 20, wherein the image processing means is further operable so that a difference of level at which the model is positioned in the virtual space is found and the action that is applied to the model is interpolated in accordance with this level difference.
25. A game device including the image processing device according to claim 19.
26. The game device according to claim 25, further comprising:
input means for controlling the movement of the models, the input means including direction keys for specifying the direction of action of a model in question vertically or horizontally, wherein the image processing means executes image processing in response to operation of the direction keys such as to effect automatic circular movement of the model.
27. A recording medium on which is recorded an image processing program adapted to control the operation of a games device in the playing of a combat type game so as to i) set up in virtual space a first model being controlled by a player and a second controlled model, wherein the first model and the second model combat each other; and ii) control the models such that they move in prescribed directions in the virtual space and to cause a display means to display images of this virtual space from a virtual viewpoint;
and to perform image processing whereby the execution of a prescribed motion operation, while the game is in progress, by a player controlling the first model causes a virtual attractive force to be set up to act between the first model and the second model and causes the first model automatically to move around the second model being a center of the virtual attractive force.