1. A storage apparatus having a controller receiving a data inputoutput request from an other apparatus and performing a data inputoutput processing to a storage volume on a storage unit, the storage apparatus comprising:
said controller controlling a data transfer between the controller and said other apparatus to perform the data inputoutput processing and including:
an inputoutput controller for controlling said data inputoutput processing;
a data transfer controller for controlling said data transfer based on an instruction of said inputoutput controller;
a first memory unit to be a transfer destination or transfer source in said data transfer; and
a second memory unit for storing data transfer information to control said data transfer,
wherein said data transfer controller includes:
a data transfer circuit for controlling a DMA (Direct Memory Access) data transfer; and
a communication interface unit having a communication interface with said other apparatus and performing a communication processing between said controller and said other apparatus, and
wherein said data transfer circuit includes a plurality of DMA units each having a DMA controller, a register for storing said data transfer information, and a buffer for storing data to be transferred, and wherein said data transfer circuit includes means for performing processes of saving and recovering data transfer information, concurrently with performing processes of data transfer, while suppressing loads caused by said saving and recovering processes of the data transfer information, comprising means for making said register of one of said DMA units and its corresponding buffer perform a process of saving, into said second memory unit, data transfer information stored in said register of said one of said DMA units and data stored in said corresponding buffer and a processing of recovering the data transfer information and the data saved in said second memory unit, means for concurrently processing one or more data transfers by using said plurality of DMA units, means for processing said data transfers by using said saving and recovering processes in one of said DMA units while said data transfers are shifted, means for multiprocessing a plurality of data transfers, and means for executing control, concurrently with said processing of said one or more data transfers by said plurality of DMA units, for saving in advance, into said second memory unit, for future data transfer, the data transfer information stored in said register and the data stored in said buffer by using one of the DMA units not currently processing said data transfers, wherein in said data inputoutput processing of said controller, said inputoutput controller starts said data transfer controller by writing, into said second memory unit, the data transfer information including a data storage position in said first memory unit and a data storage position in said other apparatus in response to receipt of data from said other apparatus or a command from said controller,
said started data transfer controller starts any of said plurality of DMA units, and
said started DMA unit controls, based on said data transfer information read from said second memory unit to said register, data transfers between said first memory unit and a third memory unit of said communication interface unit through said buffer while the saving or recovering operation is performed by said DMA unit that is not currently processing said data transfers, and
wherein said communication interface unit performs communication processing between said third memory unit and a fourth memory unit in said other apparatus.
2. The storage apparatus according to claim 1,
wherein the data transfer by said data transfer controller is controlled in a unit of each data block obtained by dividing data to be transmitted received between said other apparatus and the storage apparatus.
3. The storage apparatus according to claim 1,
wherein said controller and said other apparatus are communicably connected through one or more switches, and
said communication interface unit executes the data transfer through said switch in a unit of respective data blocks obtained by dividing objective data to be transmittedreceived between said other apparatus and the storage apparatus.
4. The storage apparatus according to claim 1,
wherein said communication interface unit has a third memory unit used in the communication processing with said other apparatus, and
said one of said DMA units executes, in said data transfer, a data transfer between said first memory unit and said third memory unit.
5. The storage apparatus according to claim 1,
wherein said controller is configured so that a third memory, in which an individual control area for saving and recovering a pair of data transfer information stored in said register for each DMA unit and data stored in said buffer is provided, is connected to said data transfer circuit, and
each of said DMA units performs said saving or recovering operation for the control areas in said third memory.
6. The storage apparatus according to claim 1,
wherein said data transfer circuit cause a first DMA unit to execute a first data transfer based on the data transfer information,
said first DMA unit recovers said first data transfer information and the data from said second memory unit and executes said first data transfer by using this, and
concurrently with said first data transfer, a second DMA unit saves in advance the data transfer information and the data stored in said register and buffer into the second memory unit.
7. The storage apparatus according to claim 1,
wherein, in response to an instruction from said inputoutput controller and in consideration of said data inputoutput request and a status of the data transfer processing, said data transfer circuit selects preferentially one or more DMA unit not processed presently from said plurality of DMA units and thereby determines the one or more DMA unit for taking charge of said data transfer, and starts the data transfer in said determined one or more DMA unit.
8. The storage apparatus according to claim 1,
wherein said controller includes:
a channel controller provided with a first circuit board on which said inputoutput controller, said data transfer controller, and said second memory unit are formed;
a cache memory provided with a second circuit board on which said first memory is formed;
a disk controller provided with a third circuit board on which a circuit reading and writing data from said cache memory to a storage area in a storage volume of said storage unit is formed; and
a connection unit interconnecting said channel controller, cache memory, and disk controller, and
wherein said data transfer circuit controls a data transfer between said cache memory and a third memory of said communication interface unit through said buffer.
9. The storage apparatus according to claim 1,
wherein said inputoutput controller includes a first processor,
said second memory unit includes a first memory into which said first processor writes said data transfer information, and a third memory used by said DMA unit,
said communication interface unit is configured to have a second processor controlling communication with said other apparatus and a second memory storing data to be transferred between said other apparatus and the communication interface unit, and
in said data transfer, said DMA unit uses the data transfer information read from said first memory, utilizes said saving and recovery to said third memory, and executes a data transfer between said first memory unit and said second memory unit.
10. The storage apparatus according to claim 1,
wherein said inputoutput controller includes a first processor,
a second memory unit includes a first memory into which said first processor writes said data transfer information and a third memory used for said saving and recovery by said DMA unit,
said communication interface unit is configured by a protocol LSI (Large Scale Integrated Circuit) controlling communication with said other apparatus while data is stored in an internal memory, and
in said data transfer, said DMA unit use the data transfer information read from said first memory, utilizes said saving and recovery to said third memory, and executes a data transfer between said first memory unit and said internal memory of said protocol LSI.
11. The storage apparatus according to claim 1,
wherein, when a second data transfer is executed by said DMA unit and said second data transfer is a data inputoutput associated with the first data transfer having been previously executed in the DMA unit and data transfer information or data necessary for executing the second data transfer is stored in said saved register and buffer, the data transfer controller uses them to execute said second data transfer without said recovering operation.
12. The storage apparatus according to claim 11,
wherein in response to receipt of data from said other apparatus or a command from said controller and in the case where the data or command is a plurality of data transfers associated with said data inputoutput, said data transfer controller makes a same DMA unit take charge of the plurality of data transfers as continuously as possible, thereby executing said plurality of data transfers without said recovering operation.
13. The storage apparatus according to claim 8,
wherein in said data inputoutput processing, said controller processes the data transfer by using said saving or recovering operation in a normal time, and
in a processing of writing together a plurality of pieces of associated data into said cache memory from the buffer of said DMA unit, said data transfer controller exercises control of reading and writing to said cache memory without the saving and recovering operations to said second memory unit whenever each piece of data in the plurality of pieces of data is accumulated from a side of said other apparatus to the buffer of said DMA unit.
14. The storage apparatus according to claim 8,
wherein in said data inputoutput processing, said controller processes a data transfer by using said saving or recovering operation in a normal time, and
in a processing of reading together a plurality of pieces of associated data from said cache memory to the buffer of said DMA unit, said data transfer controller exercises control by using the data re-read from said cache memory without the saving or recovering operation to said second memory and transfers each piece of data in the plurality of pieces of data from the buffer of said DMA unit to a side of said other apparatus whenever it transfers each of the multiple data from the buffer of the DMA unit to the side of the other device.
15. A storage apparatus having a controller receiving a data inputoutput request from an other apparatus and performing a data inputoutput processing to a storage volume on a storage unit, the storage apparatus comprising:
said controller controlling a data transfer between said other apparatus and the controller to perform the data inputoutput processing, and including a first processor for controlling said data inputoutput processing, a data transfer controller for controlling said data transfer based on an instruction of said first processor, a cache memory to be a transfer destination or transfer source in said data transfer, a first memory storing data transfer information for controlling said data transfer written by said first processor, and a third memory adapted to be used by said data transfer controller,
wherein said data transfer controller includes a data transfer circuit for controlling a DMA (Direct Memory Access) data transfer and a communication interface unit provided with a communication interface with said other apparatus and performing a communication processing between said controller and said other apparatus,
said communication interface unit includes a second processor for controlling communication with said other apparatus, and a second memory for storing data transferred between said other apparatus and the communication interface unit,
said data transfer circuit includes a plurality of DMA units each having a DMA controller, a register for storing said data transfer information, and a buffer for storing data to be transferred,
and wherein said data transfer circuit includes means for performing processes of saving and recovering data transfer information, concurrently with performing processes of data transfer, while suppressing loads caused by said saving and recovering processes of the data transfer information, comprising means for making one of said DMA units execute the data transfer between said cache memory and said second memory by using an operation of saving, to said third memory, data transfer information stored in said register and data stored in said buffer and an operation of recovering the data transfer information and the data saved in said third memory to said register and said buffer, in accordance with the data transfer information read from said first memory, and
said data transfer controller uses said plurality of DMA units to concurrently process one or more data transfers, uses said saving or recovering operation even in one of said DMA units to process said data transfer while the data transfers are switched, multiprocesses the plurality of data transfers, and executes control, concurrently with said processing of said one or more data transfers by said plurality of DMA units, for saving in advance, for future data transfer, into said third memory, the data transfer information stored in said register and the data stored in said buffer by one or more of said DMA units not currently processing said data transfer, and
wherein in said data inputoutput processing of said controller, said inputoutput controller starts said data transfer controller by writing, into said first memory, the data transfer information including a data storage position in said first memory unit and a data storage position in said other apparatus in response to receipt of data from said other apparatus or a command from said controller,
said started data transfer controller starts any of said plurality of DMA units, and
said started DMA unit controls, based on said data transfer information read from said first memory unit to said register, data transfers between said cache memory and a second memory unit of said communication interface unit through said buffer while the saving or recovering operation is performed by said DMA unit that is not currently processing said data transfers, and
wherein said communication interface unit performs communication processing between said second memory and a fourth memory in said other apparatus.
16. A storage apparatus including a storage system having a first storage apparatus provided with a first controller for receiving a data inputoutput request from an information processor and performing a data inputoutput processing to a first storage volume on a storage unit, and a second storage apparatus provided with a second controller communicably connected to said first controller and executing a data inputoutput processing to a second storage volume on the storage unit, the storage apparatus comprising:
said first controller controlling a data transfer between said information processor or second controller that is an other apparatus and the first controller to perform the data inputoutput processing to said first or second storage volume and includes:
an inputoutput controller for controlling said data inputoutput processing;
a data transfer controller for controlling said data transfer based on an instruction of said inputoutput controller;
a first memory unit to be a transfer destination or a transfer source in said data transfer; and
a second memory unit storing data transfer information for controlling said data transfer,
wherein said data transfer controller includes:
a data transfer circuit for controlling a DMA (Direct Memory Access) data transfer; and
a communication interface unit provided with a communication interface with said other apparatus and performing a communication processing between said controller and said other apparatus, and
wherein said data transfer circuit includes a plurality of DMA units each having a DMA controller, a register for storing said data transfer information, and a buffer for storing data to be transferred, and wherein said data transfer circuit includes means for performing processes of saving and recovering data transfer information, concurrently with performing processes of data transfer, while suppressing loads caused by said saving and recovering processes of the data transfer information, comprising means for making said register of one of said DMA units and it’s corresponding buffer perform a process of saving, into said second memory unit, data transfer information stored in said register of said one of said DMA units and data stored in said corresponding buffer and a processing of recovering the data transfer information and the data saved in said second memory unit, means for concurrently processing one or more data transfers by using said plurality of DMA units, means for processing said data transfers by using said saving and recovering processes in one of said DMA units while said data transfers are shifted, means for multiprocessing a plurality of data transfers, and means for executing control, concurrently with said processing of said one or more data transfers by said plurality of DMA units, for saving in advance, into said second memory unit, for future data transfers, the data transfer information stored in said register and the data stored in said buffer by using one of the DMA units not currently processing said data transfers, and
wherein in said data inputoutput processing of said controller, said inputoutput controller starts said data transfer controller by writing, into said second memory unit, the data transfer information including a data storage position in said first memory unit and a data storage position in said other apparatus in response to receipt of data from said other apparatus or a command from said controller,
said started data transfer controller starts any of said plurality of DMA units, and
said started DMA unit controls, based on said data transfer information read from said second memory unit to said register, data transfers between said first memory unit and a third memory unit of said communication interface unit through said buffer while the saving or recovering operation is performed by said DMA unit that is not currently processing said data transfers, and
wherein said communication interface unit performs communication processing between said third memory unit and a fourth memory unit in said other apparatus.
17. The storage apparatus according to claim 16,
wherein, upon receipt of a data inputoutput request to the second storage volume in said second storage apparatus from an information processor that comprises said other apparatus, said inputoutput controller writes, to said second memory unit, the data transfer information controlling a data transfer for performing the data inputoutput processing to said second storage apparatus in accordance with the reception, and
based on said data transfer information read to said register from said second memory unit, said data transfer controller controls the data transfer between said first memory unit and said second controller.
18. The storage apparatus according to claim 16,
wherein, upon receipt of a data write request and write data to said first storage volume from the information processor that is said other apparatus, said inputoutput controller writes, to said second memory unit, the data transfer information for controlling the data transfer for performing the data write processing to said first storage volume and the processing of also writing a duplication of said write data into said second storage volume in said second storage apparatus in accordance with the reception, and
based on said data transfer information read from said second memory unit to said register, said data transfer controller controls the data transfer including a transfer of said write data between said first memory unit and said second controller.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A bottom hole assembly comprising:
a rod member comprising:
a top end;
a bottom end; and
a continuous, asymmetrical passage formed in a center of the rod member, the continuous passage comprising:
an entry point disposed on the top end of the rod member;
an exit port disposed on the bottom end of the rod member; and
an intersection formed within the continuous asymmetrical passage;
wherein fluid passing through the continuous asymmetrical passage is accelerated proximate the intersection to urge the bottom hole assembly forward.
2. The bottom hole assembly of claim 1 wherein the rod member further comprises a first half and a second half.
3. The bottom hole assembly of claim 2 wherein the first half defines a first continuous groove and the second half defines a second continuous groove.
4. The bottom hole assembly of claim 3 wherein the first continuous groove and the second continuous groove form the continuous asymmetrical passage when the first half and the second half of the member are placed together.
5. The bottom hole assembly of claim 1 wherein the continuous asymmetrical passage comprises a first bend, a second bend, a first section, a second section, and a third section, wherein the first section meets the second section at the first bend and the second section meets the third section at the second bend.
6. The bottom hole assembly of claim 5 wherein the intersection is between the second section and the third section.
7. The bottom hole assembly of claim 6 wherein the width of the third section is narrower prior to the intersection.
8. The bottom hole assembly of claim 1 wherein the continuous asymmetrical passage is cylindrical.
9. The bottom hole assembly of claim 1 wherein the continuous asymmetrical passage is rectangular.
10. A method for running a drill string with a bottom hole assembly into a borehole, the bottom hole assembly comprising a top end, a bottom end, and a continuous asymmetrical passage and an intersection, the method comprising:
placing the drill string with the bottom hole assembly into the borehole;
passing a fluid through the top end of the bottom hole assembly and into the continuous asymmetrical passage;
accelerating the fluid by passing the fluid through the intersection of the continuous asymmetrical passage; and
advancing the bottom hole assembly and the drill string forward by passing the fluid through the bottom end of the bottom hole assembly.
11. The method of claim 10 further comprising the step of passing the fluid through a first bend in the continuous asymmetrical passage and through a second bend in the continuous asymmetrical passage.
12. The method of claim 10 further comprising the step of passing the fluid through a narrowed portion of the continuous asymmetrical passage prior to passing the fluid through the intersection of the continuous asymmetrical passage.
13. The method of claim 10 further comprising the step of passing fluid through the drill string and into the bottom hole assembly.
14. A fluid conveyed thruster for facilitating the insertion of a bottom hole assembly into a wellbore, the fluid conveyed thruster comprising:
a rod member, the rod member comprising:
a top end,
a bottom end,
a first half comprising a continuous groove, wherein the continuous groove comprises an intersection; and
a second half, wherein the continuous groove forms a continuous asymmetrical passage when the first half and the second half are joined; and
wherein a fluid passes through the entry point disposed on the top end of rod member, into the continuous asymmetrical passage, through the intersection, and out the exit port disposed on the bottom end of the rod member to cause the fluid conveyed thruster to advance the bottom hole assembly forward within the wellbore.
15. The fluid conveyed thruster of claim 14 wherein the second half comprises a continuous groove.
16. The fluid conveyed thruster of claim 15 wherein the continuous groove of the second half comprises an intersection.
17. The fluid conveyed thruster of claim 15 wherein the continuous groove of the second half forms a continuous asymmetrical passage when the first half and the second half are joined.
18. The fluid conveyed thruster of claim 14 wherein the continuous asymmetrical passage comprises a first bend, a second bend, a first section, a second section, and a third section, wherein the first section meets the second section at the first bend and the second section meets the third section at the second bend.
19. The fluid conveyed thruster of claim 18 wherein the intersection is between the second section and the third section.
20. The fluid conveyed thruster of claim 19 wherein the width of the third section is narrower prior to the intersection.
21. The fluid conveyed thruster of claim 14 wherein the continuous asymmetrical passage is cylindrical.
22. The fluid conveyed thruster of claim 14 wherein the continuous asymmetrical passage is rectangular.