1. An apparatus comprising:
a transconductance circuit having a positive input terminal and a negative input terminal, the transconductance circuit including:
a level shifter;
an output stage coupled to the level shifter;
a first input stage coupled to the output stage
a second input stage coupled to the output stage,
the first and second input stage each comprising a first and second darlington pair,
wherein the level shifter is a digital signal level shifter that generates a logic high signal at pump a voltage.
2. The apparatus of claim 1, wherein transconductance circuit operates using a plurality of voltage domains.
3. The apparatus of claim 1, wherein the transconductance circuit is used to drive motors or piezeoelectric transducers.
4. The apparatus of claim 1, wherein the transconductance amplifier further includes a current bias network coupled to the first and second input stages.
5. The apparatus of claim 1, wherein a differential input pair of the transconductance circuit operates in conjunction with a plurality of transistors as a folded cascode amplifier.
6. The apparatus of claim 1, wherein the first input stage includes a common mode feedback circuit wherein the inputs and outputs of input stage being shorted.
7. The apparatus of claim 1, wherein the first darlington pairs of the first and second input circuits are arranged as folded darlington pairs.
8. The apparatus of claim 1, further including:
an input network that is coupled to the positive and negative input terminals of the transconductance circuit and that receives an input signal;
a control circuit that generates a gain control signal; and
a cancellation circuit that is coupled to the positive and negative input terminals of the transconductance circuit, that is coupled to the gain control circuit, and that receives the input signal, wherein the cancellation circuit subtracts a cancellation current from the positive and negative input terminals of the transconductance circuit, and wherein the magnitude of the cancellation current is based at least in part on the gain control signal.
9. The apparatus of claim 1, wherein the cancellation circuit further comprises:
a first impedance network that receives a positive portion of the input signal that is coupled to the negative input terminal of the transconductance circuit;
a second impedance network that receives a negative portion of the input signal and that is coupled to the positive input terminal of the transconductance circuit; and
a plurality of shunt switches that are coupled between the first impedance network and the second impedance network, wherein each shunt switch is coupled to the control circuit so as to receive the gain control signal.
10. The apparatus of claim 9, wherein the control circuit receives a control voltage and linearizes the gain control signal such that the gain control signal follows the control voltage.
11. The apparatus of claim 10, wherein the control circuit further comprises:
an amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the negative input terminal of the amplifier receives the control voltage; and
an NMOS transistor that is coupled to the output terminal of the amplifier at its gate and the positive input terminal of the amplifier at its drain.
12. An apparatus comprising:
a positive input terminal for the apparatus;
a negative input terminal for the apparatus, wherein the positive and negative input terminals for the apparatus receive positive and negative portions of an input signal, respectively;
a first resistor that is coupled to the positive input terminal for the apparatus;
a second resistor that is coupled to the negative input terminal for the apparatus;
a cancellation circuit having:
a third resistor that is coupled to the positive input terminal for the apparatus;
a fourth resistor that is coupled to the negative input terminal for the apparatus;
a plurality of shunt switches that are coupled between the third resistor and the forth resistor;
a fifth resistor that is coupled to the third resistor; and
a sixth resistor that is coupled to the fourth resistor;
a control circuit that generates a gain control signal that follows a control voltage and that is coupled to provide the gain control signal to each of the shunt switches; and
a transconductance circuit having a positive input terminal and a negative input terminal, wherein the negative input terminal of the transconductance circuit is coupled to the second and sixth resistors, and wherein the positive input terminal of the transconductance circuit is coupled to the third and fifth resistors,
the transconductance circuit including:
a level shifter;
an output stage coupled to the level shifter;
a first input stage coupled to the output stage
a second input stage coupled to the output stage,
the first and second input stage each comprising a first and second darlington pair.
13. The apparatus of claim 12, wherein the transconductance circuit is used to drive motors or piezeoelectric transducers.
14. The apparatus of claim 12, wherein the first input stage includes a common mode feedback circuit wherein the inputs and outputs of input stage being shorted.
15. The apparatus of claim 12, wherein the first darlington pairs of the first and 414 are arranged as folded darlington pairs.
16. The apparatus of claim 12, wherein the plurality of shunt switches further comprises:
a first NMOS transistor that is coupled to the third resistor at its drain and the control circuit at its gate; and
a second NMOS transistor is coupled to the fourth transistor at its drain, the control circuit at its gate, and the source of the first NMOS transistor at its source.
17. The apparatus of claim 16, wherein the control circuit further comprises:
an amplifier having a positive input terminal, a negative input terminal, and an output terminal, wherein the negative input terminal of the amplifier receives the control voltage, and wherein the output terminal of the amplifier is coupled to the gates of the first and second NMOS transistors;
a third NMOS transistor that is coupled to the output terminal of the amplifier at its gate and the positive input terminal of the amplifier at its drain;
a seventh resistor that is coupled between the drain and source of the third NMOS transistor; and
a current source that is coupled to the drain of the third NMOS transistor.
18. A transconductance circuit having a positive input terminal and a negative input terminal, the transconductance circuit including:
a level shifter;
an output stage coupled to the level shifter;
a first input stage coupled to the output stage
a second input stage coupled to the output stage,
the first and second input stage each comprising a first and second darlington pair,
wherein the transconductance amplifier further includes a current bias network coupled to the first and second input stages, and
wherein a differential input pair of the transconductance circuit operates in conjunction with a plurality of transistors as a folded cascode amplifier,
wherein the transconductance circuit is further coupled to:
an input network that is coupled to the positive and negative input terminals of the transconductance circuit and that receives an input signal;
a control circuit that generates a gain control signal; and
a cancellation circuit that is coupled to the positive and negative input terminals of the transconductance circuit, that is coupled to the gain control circuit, and that receives the input signal, wherein the cancellation circuit subtracts a cancellation current from the positive and negative input terminals of the transconductance circuit, and wherein the magnitude of the cancellation current is based at least in part on the gain control signal.
19. The apparatus of claim 18, wherein the cancellation circuit further comprises:
a first impedance network that receives a positive portion of the input signal that is coupled to the negative input terminal of the transconductance circuit;
a second impedance network that receives a negative portion of the input signal and that is coupled to the positive input terminal of the transconductance circuit; and
a plurality of shunt switches that are coupled between the first impedance network and the second impedance network, wherein each shunt switch is coupled to the control circuit so as to receive the gain control signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for compressing data utilizing multiple encoders on a single integrated circuit, comprising:
receiving data in a single integrated circuit;
encoding the data utilizing a plurality of encoders incorporated on the single integrated circuit.
2. The method as recited in claim 1, wherein the data is encoded utilizing multiple channels on the single integrated circuit.
3. The method as recited in claim 1, wherein the data is encoded into a wavelet-based format.
4. A single integrated circuit for compressing data, comprising:
a first encoder embodied on the single integrated circuit for encoding a first set of data; and
a second encoder embodied on the same single integrated circuit as the first encoder for encoding a second set of data.
5. The single integrated circuit as recited in claim 4, wherein the data is encoded utilizing multiple channels on the single integrated circuit.
6. The single integrated circuit as recited in claim 4, wherein the data is encoded into a wavelet-based format.
7. A method for compressing data utilizing a single module, comprising:
receiving photons utilizing a single module; and
outputting compressed data representative of the photons utilizing the single module.
8. The single module as recited in claim 7, wherein the compressed data is encoded into a wavelet-based format.
9. The single module as recited in claim 8, wherein transform operations associated with the encoding are carried out in analog.
10. The single module as recited in claim 7, wherein the single module includes an imager.