1. A test environment for verifying a design of a semiconductor device including a central processing unit and an interface system operatively connected to said central processing unit, the test environment comprising:
a transaction generator configured to generate a stream of transactions;
a translator unit operatively connected to said transaction generator to receive said stream of transactions therefrom, said translator unit being configured to provide a machine code representation for each of said transactions to provide executable instructions for said central processing unit to operate said central processing unit in its native mode;
a machine code interface configured to receive said machine code representations and to enable access to at least some of said machine code representations by said central processing unit; and
a transaction check unit configured to receive and verify a response transaction representing a response of said central processing unit, said transaction check unit being further configured to compare the received response and a reference model representing an expected behavior of the at least one of said central processing unit.
2. The test environment of claim 1, wherein said transaction check unit is further configured to verify CPU transactions, wherein said CPU is at least one of a target and a source of said CPU transactions.
3. The test environment of claim 1, further comprising a test control unit operatively connected to said transaction generator and configured to control said transaction generator to provide said stream of transactions as a randomly constrained stream of transactions.
4. The test environment of claim 3, wherein said transaction check unit is operatively connected to said test control unit and wherein said test control unit is further configured to control said transaction generator on the basis of information provided by said transaction check unit.
5. The test environment of claim 1, further comprising a secondary interface that is connected to said transaction check unit.
6. The test environment of claim 5, wherein said secondary interface is not directly accessible by said CPU.
7. The test environment of claim 5, wherein said secondary interface is a part of a peripheral block.
8. The test environment of claim 1, further comprising a memory module accessible by said central processing unit via a memory controller, said memory module being configured to receive said machine code representations from said machine code interface.
9. The test environment of claim 1, further comprising a memory module configured to receive said machine code representations from said machine code interface, and a memory interface connected to said memory module and configured to be connectable to said interface system to enable said central processing unit to access said memory module via said interface system and said memory interface.
10. The test environment of claim 1, further comprising a memory module accessible by said transaction generator, wherein said translator unit is connected to said memory module and said machine code interface is configured to be accessible by a memory controller.
11. The test environment of claim 1, further comprising a memory module accessible by said central processing unit via said interface system and a memory controller connected thereto, wherein said machine code interface is configured to store said machine code representations in said memory module via said interface system.
12. The test environment of claim 1, further comprising a monitor module configured to convert bus signal waveforms into transactions, wherein said monitor module is connected to said transaction check unit so as to receive a response from said interface system.
13. A method of performing a transaction-based verification of a semiconductor device in a design state, the method comprising:
creating a first plurality of transactions representing communication events between a central processing unit and a peripheral functional block of said semiconductor device;
generating machine code instructions from said first plurality of transactions, said machine code instructions containing at least some instructions executable by said central processing unit;
supplying said at least some executable instructions to said central processing unit to operate said central processing unit in its native mode; and
checking a response of at least one of said peripheral functional block and the central processing unit to obtain verification information, said response being caused by executing said at least some instructions by said central processing unit, wherein checking the response includes comparing the response with a reference model representing an expected behavior of said at least one of said peripheral functional block and the central processing unit.
14. The method of claim 13, further comprising creating a second plurality of transactions by adapting the first plurality of transaction on the basis of said verification information and generating machine code instructions from said second plurality of transactions.
15. The method of claim 13, wherein checking a response of at least said peripheral functional block comprises obtaining data of said peripheral functional block on a signal level, converting said data into a transaction level and evaluating said data on said transaction level.
16. The method of claim 13, wherein creating said first plurality of transactions comprises creating said first plurality of transactions by using a randomizing mechanism.
17. The method of claim 13, wherein generating said machine code instructions and enabling access by said central processing unit comprises storing said machine code instructions in a memory module accessible by said central processing unit and causing said central processing unit to access said memory module.
18. The method of claim 17, wherein said memory module is accessed via a memory controller of said semiconductor device.
19. The method of claim 17, further comprising providing an interface module that is configured to communicate with an internal interface system of said semiconductor device and accessing said memory module via said interface module.
20. The method of claim 13, wherein generating said machine code instructions and enabling access by said central processing unit comprises storing said first plurality of transactions in a memory module and converting transactions into machine code instructions and machine code instructions into transactions when accessing said memory module by said central processing unit.
21. The method of claim 13, wherein generating said machine code instructions and enabling access by said central processing unit comprises storing said machine code instructions in a memory module via an internal interface system and a memory controller of said semiconductor device.
22. The method of claim 13, further comprising performing a transaction-based verification process for verifying a functional behavior of said functional peripheral block.
23. The method of claim 13, wherein at least some components of said semiconductor device are provided in the form of a re-configurable representation.
24. The method of claim 13, wherein said peripheral functional block comprises an embedded functional block operatively connected to said central processing unit by a device internal interface system.
25. The method of claim 13, further comprising incorporating self-test code into said sequence of transactions and storing a machine code version of said self-test code in a memory model.
26. The method of claim 25, further comprising providing the reference model for said self-test code.
27. The method of claim 25, wherein said self-test code is configured to detect design errors.
28. The method of claim 27, further comprising simulating a behavior of a destination environment of said semiconductor device and using said machine code version of said self-test code for performing a self-test.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. An optical transceiver comprising;
a multi-direction variable transmitter; and
a multi-direction variable receiver
wherein said transmitter includes multiple outputs with different subcarriers being directed to different ones of the outputs to go to different directions in a network, the receiver includes receiving multiple inputs, thereby enabling transmission direction in a network with the transceiver at subcarrier granularity and avoiding entire super-channel granularity and enabling unused subcarriers to be utilized for traffic in other directions or destinations and making switching granularity finer for flexibility in the network.
2. The transceiver of claim 1, wherein the transmitter comprises a subcarrier aggregator including multiple ones of the outputs from modulators within the transmitter.
3. The transceiver of claim 2, wherein the subcarrier aggregator comprises directing each of a modulated subcarrier to respective ones of the outputs and to combine multiple subcarriers at each output.
4. The transceiver of claim 2, wherein the subcarrier aggregator comprises, after passing through the subcarrier aggregator, each output having a super-channel signal with different subcarrier arrangements and different outputs being sent to different directions in the network.
5. The transceiver of claim 2, wherein the subcarrier aggregator comprises the number of subcarriers and the configuration in each subcarrier being changeable and the output of each subcarrier being changeable.
6. The transceiver of claim 2, wherein the subcarrier aggregator comprises a subcarrier multiplexer for receiving multiple subcarrier inputs and coupled to a wavelength-selective switch providing the outputs of the subcarrier aggregator.
7. The transceiver of claim 2, wherein the subcarrier aggregator comprises multiple 1\xd7M optical switches for receiving multiple subcarrier inputs and coupled to multiple 1\xd7M switches in parallel with output ports being connected to input ports of respective subcarriers multiplexers in parallel.
8. The transceiver of claim 2, wherein the subcarrier aggregator comprises subcarrier multiplexers for receiving multiple subcarrier inputs separated into odd and even subcarrier groups and coupled to respective flexible grid switches which select the output port for each subcarrier.
9. The transceiver of claim 1, wherein the receiver comprises inputs for receiving input signals from multiple directions each carrying different combinations of super-channel subcarriers and a subcarrier combiner for combining the multiple ones of the inputs to form a super-channel, the receiver employing network control and subcarrier allocation that avoids contention among different ones of the inputs.
10. A method by a transceiver in an optical network comprising the steps of:
a multi-direction variable transmitter including multiple outputs with different subcarriers for directing different ones of the outputs to go to different directions in the network; and
a multi-direction variable receiver for receiving multiple input, for enabling transmission direction in the network with the transceiver at subcarrier granularity and avoiding entire super-channel granularity and for enabling unused subcarriers to be utilized for traffic in other directions or destinations and making switching granularity finer for flexibility in the network.
11. The method of claim 10, wherein the transmitter comprises a subcarrier aggregator including multiple ones of the outputs from modulators within the transmitter.
12. The method of claim 12, wherein the subcarrier aggregator comprises directing each of a modulated subcarrier to respective ones of the outputs and to combine multiple subcarriers at each output.
13. The method of claim 12, wherein the subcarrier aggregator comprises, after passing through the subcarrier aggregator, each output having a super-channel signal with different subcarrier arrangements and different outputs being sent to different directions in the network.
14. The method of claim 12, wherein the subcarrier aggregator comprises the number of subcarriers and the configuration in each subcarrier being changeable and the output of each subcarrier being changeable.
15. The method of claim 12, wherein the subcarrier aggregator comprises a subcarrier multiplexer for receiving multiple subcarrier inputs and coupled to a wavelength-selective switch providing the outputs of the subcarrier aggregator.
16. The method of claim 12, wherein the subcarrier aggregator comprises multiple 1\xd7M optical switches for receiving multiple subcarrier inputs and coupled to multiple 1\xd7M switches in parallel with output ports being connected to input ports of respective subcarriers multiplexers in parallel.
17. The method of claim 12, wherein the subcarrier aggregator comprises subcarrier multiplexers for receiving multiple subcarrier inputs separated into odd and even subcarrier groups and coupled to respective flexible grid switches which select the output port for each subcarrier.
18. The method of claim 10, wherein the receiver comprises inputs for receiving input signals from multiple directions each carrying different combinations of super-channel subcarriers and a subcarrier combiner for combining the multiple ones of the inputs to form a super-channel, the receiver employing network control and subcarrier allocation that avoids contention among different ones of the inputs.