1. An electrical connector comprising:
a housing having a terminal supporting member and a space at a base portion of the terminal supporting member;
a plurality of terminals attached to the housing and arranged on the terminal supporting member in parallel;
a latch member arranged on the terminal supporting member in parallel to the terminals for locking a mating connector; and
a housing cover attached to the housing for covering a part of the housing, said housing cover including a cylindrical portion for covering the terminal supporting member, said cylindrical portion including a base portion held in the space.
2. The electrical connector according to claim 1, wherein said terminal supporting member extends in a first direction toward the mating connector, said terminals and said latch member being arranged along the first direction.
3. The electrical connector according to claim 1, wherein said housing includes the space extending toward inside the housing.
4. The electrical connector according to claim 2, wherein said housing further includes thick wall portions extending at left and right sides of the terminal supporting member along the first direction so that the space surrounds at least circumferences of the thick wall portions.
5. The electrical connector according to claim 1, wherein said terminal supporting member includes one surface facing the space and the other surface opposite to the one surface with the terminals arranged thereon.
6. The electrical connector according to claim 1, wherein each of said terminals includes a contact piece arranged on the terminal supporting member in a state that a substantially upper half thereof is exposed.
7. The electrical connector according to claim 6, wherein said housing further includes an upper surface having terminal holes for exposing the contact pieces; a latch receiving portion for receiving the latch member; and a lower supporting column so that the space surrounds a whole circumference of the housing except the upper surface, the latch receiving portion, and the lower supporting column.
8. The electrical connector according to claim 2, wherein said cylindrical portion includes a slit opened at the base portion of the cylindrical portion and closed at a front portion thereof, said slit extending along the first direction.
9. The electrical connector according to claim 1, wherein said terminal supporting member is integrated with the housing.
10. The electrical connector according to claim 1, wherein said housing cover further includes a first cover portion having the cylindrical portion and a second cover portion separate from the first cover portion.
11. The electrical connector according to claim 1, wherein said housing cover is formed of one metal plate punched out and bent.
12. The electrical connector according to claim 1, wherein said terminal supporting member has a plate shape.
13. The electrical connector according to claim 2, wherein said cylindrical portion includes a protruding portion extending in a direction perpendicular to the first direction.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A mass storage device comprising:
a host bus adaptor configured to emulate a SATA device over a PCIe link; and
a SATA storage device, coupled to the host bus adaptor, configured to respond to SATA commands from the host bus adaptor.
2. The device of claim 1 wherein the SATA storage device is a solid state drive.
3. The device of claim 2 wherein the solid state drive is comprised of one of flash memory, MRAM, or 3D memory.
4. The device of claim 1 wherein the SATA storage device is one of an optical drive or a magnetic disk drive.
5. The device of claim 1 wherein the host bus adaptor comprises an Advanced Host Control Interface (AHCI) Host Bus Adaptor (HBA) emulator.
6. The device of claim 5 wherein the AHCI HBA emulator comprises a hardware interface configured to interface host system software with the SATA storage device.
7. The device of claim 1 wherein the SATA storage device comprises storage media configured to store data and a media manager coupled to the storage media for controlling operations of the storage media.
8. A PCIe mass storage device comprising:
an Advanced Host Control Interface (AHCI) Host Bus Adaptor (HBA) emulator configured to emulate a SATA HBA over a PCIe link; and
storage media for storing and retrieving data in response to the AHCI HBA, the storage media comprising a media manager configured to control operation of the storage media.
9. The device of claim 8 wherein the AHCI HBA emulator comprises:
a PCIe physical layer configured to interface the mass storage device to the PCIe link;
a PCIe Core, coupled to the PCIe physical layer, configured to encodedecode PCIe packets;
a PCIe-to-AHCI Bridge, coupled to the PCIe Core, configured to translate PCIe data to SATA format data and SATA format data to PCIe data;
an AHCI engine, coupled to the PCIe-to-AHCI Bridge, configured to act as a bus master between a host memory and the PCIe mass storage device; and
a SATA device, coupled to the AHCI engine, configured to provide SATA emulation for the PCIe mass storage device.
10. The device of claim 9 wherein the PCIe physical layer is configured to down-convert PCIe data from a PCIe link data rate to a lower data rate for the PCIe mass storage device and up-convert SATA data from the lower data rate to the PCIe link data rate.
11. The device of claim 9 wherein the AHCI engine performs direct memory access operations between the host memory and the PCIe mass storage device.
12. The device of claim 9 wherein the PCIe physical layer is configured to convert analog PCIe signals to digital SATA signals and the PCIe physical layer is further configured to convert digital SATA signals to analog PCIe signals.
13. The device of claim 9 wherein the PCIe physical layer further comprises buffers for temporary storage of incoming and outgoing data.
14. The device of claim 9 wherein the PCIe physical layer is comprised of a hardware function.
15. The device of claim 9 wherein the AHCI Engine comprises:
a direct memory access write engine configured to perform direct memory access write operations to host memory;
a direct memory access read engine configured to perform direct memory access read operations from the host memory; and
AHCI registers that configure and control the PCIe mass storage device.
16. The device of claim 9 wherein the PCIe-to-AHCI Bridge, the AHCI Engine, and the SATA device comprise an AHCI device controller that provides data movement between host memory and the storage media.
17. The device of claim 8 wherein the storage media comprises a solid state drive and the media manager generates control signals for reading, writing, and erasing the solid state drive.
18. A method for operating a PCIe mass storage device, the method comprising:
instructing a host that the PCIe mass storage device is a SATA host bus adaptor;
receiving communication in a SATA format; and
emulating the SATA format.
19. The method of claim 18 wherein instructing the host that the PCIe mass storage device is a SATA host bus adaptor comprises instructing the host that a PCIe mass storage device coupled to the host over a PCIe interface is a SATA host bus adaptor.
20. The method of claim 18 and further comprising receiving configuration data in configuration registers in the PCIe mass storage device, the configuration data being in a SATA format.
21. The method of claim 18 and further comprising transmitting, in a SATA format, status data regarding operational status of the PCIe mass storage device.
22. A PCIe mass storage system comprising:
a host system configured to control operations of the mass storage system; and
a PCIe mass storage device coupled to the host system over a PCIe interface, the mass storage device comprising:
a host bus adaptor configured to emulate a SATA device with the host system; and
a SATA mass storage device coupled to the host bus adaptor and configured to respond to SATA commands from the host system.
23. The system of claim 22 wherein the host system is a computer having a PCIe link circuit.
24. The system of claim 22 wherein the host system comprises software configured to communicate in a SATA format.
25. The system of claim 23 wherein the computer comprises an operating system with a capability of communicating with a SATA mass storage device over the PCIe interface.
26. The system of claim 22 wherein the PCIe mass storage device is coupled to the host system without a PCIe-to-SATA bridge.
27. A mass storage device comprising:
a host bus adaptor configured to emulate a first interface device over a second interface link, wherein the first interface and second interface are different interface standards; and
a first interface storage device, coupled to the host bus adaptor, configured to respond to first interface commands from the host bus adaptor.