1. A digital phase comparator comprising:
a first circuit unit including a first delay element array delaying a first clock signal at regular intervals, and a first group of data holding circuits generating and producing first phase difference signals obtained by sampling a second clock signal with the use of the first clock signal and a first group of delayed signals obtained by delaying the first clock signal with the first delay element array;
a second circuit unit generating a first signal by performing a logic operation on the first phase difference signals; and
a third circuit unit including a second delay element array delaying the second clock signal at first regular intervals, and a third delay element array delaying the first signal at second regular intervals, and further including a second group of data holding circuits for generating and producing second phase difference signals obtained by sampling a second group of delayed signals obtained by delaying the second clock signal with the second delay element array, with the uses of a third group of delayed signals obtained by delaying the first signal with the third delay element array,
wherein the first phase difference signals and the second phase difference signals are digital phase difference information indicating a phase difference between the first clock signal and the second clock signal.
2. The digital phase comparator as claimed in claim 1, wherein the first signal is a signal in synchronism with a delayed signal in the first group of delayed signals, that is produced immediately after the transition of the second clock signal.
3. The digital phase comparator as claimed in claim 1, wherein the first signal is a signal which rises in synchronism with a delayed signal in the first group of delayed signals, that is produced immediately after the rising of the second clock signal, and which falls in synchronism with a delayed signal in the first group of delayed signals, that is produced immediately after the falling of the second clock signal.
4. The digital phase comparator as claimed in claim 1, wherein the third circuit unit further includes a third group of data holding circuits, and, in the third circuit unit, the second group of data holding circuits produce second phase difference signals for the rising edge obtained by sampling the second group of delayed signals at the rising edges of the third group of delayed signals, and the third group of data holding circuits produce second phase difference signals for the falling edge obtained by sampling the second group of delayed signals at the falling edges of the third group of delayed signals.
5. The digital phase comparator as claimed in claim 4, wherein the second phase difference signals sampled in the third circuit unit are used for further correcting the phase difference between the first clock signal and the second clock signal that has been corrected with the first phase difference signals sampled in the first circuit unit.
6. The digital phase comparator as claimed in claim 1, further comprising a fourth circuit unit generating a second signal by performing a predetermined logic operation on the second clock signal, the second signal being supplied to the third circuit unit in place of the second clock signal.
7. The digital phase comparator as claimed in claim 6, wherein the setting is such that a delay time from when a delayed signal in the first group of delayed signals, that is produced immediately after the transition of the second clock signal, is supplied until when the first signal is produced in the second circuit unit is equal to a delay time from when the second clock signal is supplied until when the second signal is produced in the fourth circuit unit.
8. The digital phase comparator as claimed in claim 6, wherein the second signal rises in synchronism with the rising edge of the second clock signal immediately after the rising of the first clock signal, and falls in synchronism with the falling edge of the second clock signal immediately after the rising of the first clock signal.
9. The digital phase comparator as claimed in claim 6, wherein:
the first signal is a signal generated by performing an exclusive OR operation on a first step signal which rises in synchronism with a delayed signal in the first group of delayed signals, that is produced immediately after the rising of the second clock signal, and a second step signal which rises in synchronism with a delayed signal in the first group of delayed signals, that is produced immediately after the falling of the second clock signal; and
the second signal is a signal generated by performing an exclusive OR operation on a step signal which rises in synchronism with the rising of the second clock signal, and a step signal which rises in synchronism with the falling of the second clock signal.
10. The digital phase comparator as claimed in claim 6, comprising:
a first data holding circuit generating a third step signal in synchronism with the falling edge of a delayed signal which is any one selected from the first group of delayed signals;
a second data holding circuit generating a fourth step signal in synchronism with the falling edge of a signal obtained by delaying the delayed signal;
a first selector circuit for selecting one of the first signal and the fourth step signal according to whether the first clock signal is at a high level or a low level; and
a second selector circuit for selecting either the second clock signal or the second signal, or the third step signal according to whether the first clock signal is at high level or a low level,
wherein, when the first clock signal is at a low level, the third and fourth step signals are selected as inputs of the third circuit unit, and sampled results in the third circuit unit are used as a value corresponding to the delay time of delay elements in the first delay element array.
11. The digital phase comparator as claimed in claim 10, wherein in the third circuit unit, the second phase difference signals sampled during a period when the first clock signal is at a high level or a low level are used to further correct a phase difference between the first clock signal and the second clock signal that has been corrected with first phase difference signals sampled in the first circuit unit.
12. The digital phase comparator as claimed in claim 10, wherein a phase difference between the first clock signal and the second clock signal is normalized with one cycle of the second clock signal with the use of the first phase difference signals sampled in the first circuit unit and the second phase difference signals sampled in the third circuit unit during periods when the first clock signal is at a high level and a low level.
13. The digital phase comparator as claimed in claim 1, comprising a fifth circuit unit generating a control signal by performing a predetermined logic operation on the first clock signal and a final delayed signal in the first group of delayed signals, the control signal being used to control whether the second clock signal is allowed to pass or stopped.
14. The digital phase comparator as claimed in claim 9, comprising a sixth circuit unit generating a control signal by performing a predetermined logic operation on the first clock signal, the first step signal, and the second step signal, the control signal being used to control whether the second clock signal is allowed to pass or stopped.
15. The digital phase comparator as claimed in claim 1, wherein the delay elements of the first to third delay element arrays are inverters.
16. The digital phase comparator as claimed in claim 10, wherein the data holding circuits in the first to third groups of data holding circuits, and the first and second data holding circuits are flip-flops.
17. A method of detecting a phase difference in a digital phase comparator, comprising:
sampling a second clock signal with the use of a first group of clock signals obtained by delaying a first clock signal at regular intervals and the first clock signal, and holding the sampled signals as first phase difference signals in a first group of data holding circuits;
generating a first signal by performing a logic operation on the first phase difference signals;
delaying the second clock signal and the first signal by different delay times from each other at regular intervals, respectively, sampling a second group of clock signals obtained by delaying the second clock signal at the regular intervals with a first group of signals obtained by delaying the first signal at the regular intervals, and holding the sampled signals as second phase difference signals in a second group of data holding circuits.
18. The method as claimed in claim 17, wherein producing, as the first signal, a signal in the first group of clock signals or the first clock signal, that is synchronous with a delayed signal produced immediately after the transition of the second clock signal.
19. The method as claimed in claim 17, wherein producing, as the first signal, a signal in the first group of clock signals or the first clock signal, that rises in synchronism with a delayed signal produced immediately after the rising of the second clock signal, and that falls in synchronism with a delayed signal produced immediately after the falling of the second clock signal.
20. The method as claimed in claim 17, wherein the step of holding in the second group of data holding circuits generates second phase difference signals for the rising edges obtained by sampling the second group of clock signals delayed at the regular intervals at the rising edges of the first group of signals delayed at the regular intervals, and second phase difference signals for the falling edges obtained by sampling the second group of clock signals at the falling edges of the group of first signals.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A cutter grinder for grinding a blade of a cutter, comprising:
a base having a rectangular deck on a top thereof, a plurality of positioning bits being disposed on both sides of the deck, with a spacing being provided between the positioning bits and both sides of the deck;
a mobile base plate covering the deck and being retained in position by both sides of the deck and the positioning bits to prevent the mobile base plate from being easily disengaged from the deck, the mobile base plate having a top surface having a dimension substantially identical to that of the deck of the base, the mobile base plate being adapted to be covered with a piece of emery cloth of a given dimension, both the emery cloth and the mobile base plate being holdable in position by the spacing between the positioning bits and both sides of the deck, the emery cloth being firmly positionable on the mobile base plate and being removable to allow for a replacement with a new emery cloth or another one with a different roughness; and
a cutter holder comprised of a frame adapted to be gripped, the cutter being positionable in the frame, a packing bolt disposed at a top of the frame; the cutter being securable to the frame using the packing bolt, an axial base extending from a bottom of the frame, and a roller axially provided on the axial base, the cutter holder being movable back and forth on the top surface of the mobile base plate while rolling on the roller to grind the blade of the cutter.
2. The cutter grinder of claim 1, wherein the mobile base plate comprises a first mobile base plate; further comprising a second mobile base plate that replaces the first mobile base plate, the second mobile base plate having a top surface having a plurality of through holes, emery being inlaid on an inside of each through hole to constitute the grinding surface in place of the emery cloth.
3. A cutter grinder, comprising:
a base having a rectangular deck, a plurality of positioning bits being disposed on both sides of the deck, with a spacing being provided between the positioning bits and both sides of the deck, the base further including a sink disposed at one end thereof and adjacent to the deck, the sink being adapted to contain a liquid and being disposed at a level higher than a top surface of the deck;
a mobile base plate covering the deck and being retained in position by both sides of the deck and the positioning bits, the mobile base plate having an upper surface having a dimension substantially identical to that of the deck of the base, and a piece of emery cloth of a given size covering the mobile base plate to define a grinding surface;
a cutter holder comprised of a frame adapted to be gripped, a cutter being positionable in the frame, a packing bolt disposed at a top of the frame; the cutter being securable to the frame using the packing bolt, an axial base extending from a bottom of the frame, and a roller being axially provided to on the axial base, the cutter holder being movable back and forth on the top surface of the mobile base plate while rolling on the roller to grind the blade of the cutter against the emery cloth; and
angle adjustment means disposed on the deck of the base for adjusting a grinding angle of a blade of the cutter, a preferred grinding angle being attained by positioning the roller of the cutter holder to rest against a sidewall of the sink, and positioning the blade of the cutter against an angle adjustment device, while the packing bolt is loosened.
4. The cutter grinder of claim 3, wherein the angle adjustment device is mounted to the deck of the base and is arranged depending on a trigonometric function value defined by the cutter holder, the cutter, and the deck.