1. A semiconductor device performing drive control of first and second switching devices connected in series and interposed between a high main power potential and a low main power potential, comprising:
a high potential part including a control part configured to control conductionnon-conduction of a high side switching device which is one of said first and second switching devices;
a low side logic circuit provided in a low potential part operating on the basis of said low main power potential and configured to generate a control signal on the basis of a signal applied from outside, said control signal having a first state indicating conduction of said high side switching device and a second state indicating non-conduction of said high side switching device, and to generate first and second pulse signals on the basis of said control signal in correspondence with said first and second states, respectively;
first and second level shift parts configured to level-shift said first and second pulse signals to said high potential part to obtain first and second level-shifted pulse signals, respectively; and
a voltage detecting device provided in said low potential part and configured to detect a potential at an output line of at least one of said first and second level shift parts and to supply a logic value based on the potential for said low side logic circuit, thereby controlling an operation of said low side logic circuit.
2. The semiconductor device according to claim 1, wherein
said voltage detecting device includes:
at least one of a field oxide film and an interlayer insulating film provided in an upper portion of a semiconductor region which forms a channel region during device operation, as a gate insulating film; and
at least one MOS transistor having said output line provided on said gate insulating film as a gate electrode.
3. The semiconductor device according to claim 2, wherein
said at least one MOS transistor includes an odd number of MOS transistors equal to or greater than three connected in parallel, and
said control signal is controlled on the basis of a logic value which is the majority of outputs of said odd number of MOS transistors.
4. The semiconductor device according to claim 2, wherein
said at least one MOS transistor includes an NMOS transistor and a PMOS transistor constituting a complementary MOS transistor,
said NMOS transistor and said PMOS transistor have said output line as a common gate electrode, and
a logic value of an output of said complementary MOS transistor is supplied to said low side logic circuit.
5. The semiconductor device according to claim 2, wherein
said at least one MOS transistor includes a plurality of MOS transistors connected in parallel, and
said plurality of MOS transistors have different threshold voltages from each other.
6. The semiconductor device according to claim 2, wherein
in said at least one MOS transistors, a semiconductor region including said channel region is electrically insulated from a semiconductor substrate, and
a bias voltage is applied to said semiconductor region to change a potential at said semiconductor region, thereby causing a threshold voltage of said at least one MOS transistor to electrically vary.
7. A semiconductor device performing drive control of first and second switching devices connected in series and interposed between a high main power potential and a low main power potential, comprising:
a high potential part including a control part configured to control conductionnon-conduction of a high side switching device which is one of said first and second switching devices;
a reverse level shift part configured to level-shift a signal from said high potential part to supply the level-shifted signal to a low side logic circuit operating on the basis of said low main power potential; and
a voltage detecting device provided in said high potential part and configured to detect a potential at an output line of said reverse level shift part and to supply a logic value based on said potential for said control part, thereby causing said control part to control conductionnon-conduction of said high side switching device.
8. The semiconductor device according to claim 7, wherein
said voltage detecting device includes:
at least one of a field oxide film and an interlayer insulating film provided in an upper portion of a semiconductor region which forms a channel region during device operation as a gate insulating film; and
at least one MOS transistor having said output line provided on said gate insulating film as a gate electrode.
9. The semiconductor device according to claim 8, wherein
said at least one MOS transistor includes an odd number of MOS transistors more than two connected in parallel, and
said control signal is controlled on the basis of a logic value which is the majority of outputs of said odd number of MOS transistors.
10. The semiconductor device according to claim 8, wherein
said at least one MOS transistor includes an NMOS transistor and a PMOS transistor constituting a complementary MOS transistor,
said NMOS transistor and said PMOS transistor have said output line as a common gate electrode, and
a logic value of an output of said complementary MOS transistor is supplied to said low side logic circuit.
11. The semiconductor device according to claim 8, wherein
said at least one MOS transistor includes a plurality of MOS transistors connected in parallel, and
said plurality of MOS transistors have different threshold voltages from each other.
12. The semiconductor device according to claim 8, wherein
in said at least one MOS transistor, a semiconductor region including said channel region is electrically insulated from a semiconductor substrate, and
a bias voltage is applied to said semiconductor region to change a potential at said semiconductor region, thereby causing a threshold voltage of said at least one MOS transistor to electrically vary.
13. A semiconductor device performing drive control of first and second switching devices connected in series and interposed between a high main power potential and a low main power potential, comprising:
a high potential part including a control part configured to control conductionnon-conduction of a high side switching device which is one of said first and second switching devices;
a low side logic circuit provided in a low potential part operating on the basis of said low main power potential and configured to generate a control signal on the basis of a signal applied from outside, said control signal having a first state indicating conduction of said high side switching device and a second state indicating non-conduction of said high side switching device, and to generate first and second pulse signals on the basis of said control signal in correspondence with said first and second states, respectively; and
a voltage detecting device provided in said low potential part and configured to detect a potential at an output line extending out of said high potential part outputting said high main power potential and to supply a logic value based on said potential for said low side logic circuit, thereby controlling an operation of said low side logic circuit.
14. The semiconductor device according to claim 13, wherein
said voltage detecting device is provided in a non-provided region of said low potential part where a semiconductor device operating on the basis of said low main power potential is not provided.
15. The semiconductor device according to claim 13, wherein
said voltage detecting device includes:
at least one of a field oxide film and an interlayer insulating film provided in an upper portion of a semiconductor region which forms a channel region during device operation as a gate insulating film; and
at least one MOS transistor having said output line provided on said gate insulating film as a gate electrode.
16. The semiconductor device according to claim 15, wherein
said at least one MOS transistor includes an odd number of MOS transistors more than two connected in parallel, and
said control signal is controlled on the basis of a logic value which is the majority of outputs of said odd number of MOS transistors.
17. The semiconductor device according to claim 15, wherein
said at least one MOS transistor includes an NMOS transistor and a PMOS transistor constituting a complementary MOS transistor,
said NMOS transistor and said PMOS transistor have said output line as a common gate electrode, and
a logic value of an output of said complementary MOS transistor is supplied to said low side logic circuit.
18. The semiconductor device according to claim 15, wherein
said at least one MOS transistor includes a plurality of MOS transistors connected in parallel, and
said plurality of MOS transistors have different threshold voltages from each other.
19. The semiconductor device according to claim 15, wherein
in said at least one MOS transistor, a semiconductor region including said channel region is electrically insulated from a semiconductor substrate, and
a bias voltage is applied to said semiconductor region to change a potential at said semiconductor region, thereby causing a threshold voltage of said at least one MOS transistor to electrically vary.
20. A semiconductor device performing drive control of first and second switching devices connected in series and interposed between a high main power potential and a low main power potential, comprising:
a high potential part including a control part configured to control conductionnon-conduction of a high side switching device which is one of said first and second switching devices; and
a voltage detecting device provided in said high potential part and inserted between said high main power potential and a node between said first and second switching devices, said voltage detecting device being configured to detect a potential at said node between said first and second switching devices and to supply a logic value based on said potential for said control part, thereby causing said control part to control conductionnon-conduction of said high side switching device, wherein
said voltage detecting device includes at least one MOS transistor whose conductionnon-conduction is controlled on the basis of a potential at an output line extending out of said low potential part outputting said low main power potential.
21. The semiconductor device according to claim 20, wherein
said voltage detecting device is provided in a non-provided region of said high potential part where a semiconductor device operating on the basis of said high side main power potential is not provided.
22. The semiconductor device according to claim 20, wherein
said voltage detecting device includes:
at least one of a field oxide film and an interlayer insulating film provided in an upper portion of a semiconductor region which forms a channel region during device operation as a gate insulating film; and
at least one MOS transistor having said output line provided on said gate insulating film as a gate electrode.
23. The semiconductor device according to claim 22, wherein
said at least one MOS transistor includes an odd number of MOS transistors more than two connected in parallel, and
said control signal is controlled on the basis of a logic value which is the majority of outputs of said odd number of MOS transistors.
24. The semiconductor device according to claim 22, wherein
said at least one MOS transistor includes an NMOS transistor and a PMOS transistor constituting a complementary MOS transistor,
said NMOS transistor and said PMOS transistor have said output line as a common gate electrode, and
a logic value of an output of said complementary MOS transistor is supplied to said low side logic circuit.
25. The semiconductor device according to claim 22, wherein
said at least one MOS transistor includes a plurality of MOS transistors connected in parallel, and
said plurality of MOS transistors have different threshold voltages from each other.
26. The semiconductor device according to claim 22, wherein
in said at least one MOS transistor, a semiconductor region including said channel region is electrically insulated from a semiconductor substrate, and
a bias voltage is applied to said semiconductor region to change a potential in said semiconductor region, thereby causing a threshold voltage of said at least one MOS transistor to electrically vary.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A reproducing method for reproducing data from a record medium in which data has been recorded thereon by: sectoring program data in terms of a pre-set data volume as a unit; data-appending copy management information, including copy generation data that specifies the copy generation of program data recorded on the record medium, and copy permitinhibit data that specifies whether or not copying is permitted up to a certain copy generation; error correction coding the sectored program data together with the data-appended copy management information; modulating the error correction coded program data together with the data-appended copy management information; and recording the modulated program data and the modulated data-appended copy management information in a pre-set position in each sector on the record medium, said reproducing method comprising:
reading the modulated program data and modulated data-appended copy management information from the record medium;
demodulating the modulated program data and modulated data-appended copy management information read from the record medium;
error correction decoding the program data together with the data-appended copy management information demodulated in the demodulating step; and
permitting or prohibiting copying of the error correction decoded program data in accordance with the error correction decoded copy management information,
wherein said sectoring of program data results in at least sectors of a 4-byte synchronization area, a header data area including an error detection code area and said copy management information, a user data area consisting of 2048-byte data, and a second error detection data area consisting of 4-byte data, said second error detection data generated for said header data area and said user data area, and
wherein the data-appending copy management information comprises the copy permitinhibit data that specifies whether or not copying is permitted up to the certain copy generation.
2. The method of claim 1, wherein said data-appended copy management information is located in a header area position in each sector.
3. An apparatus for reproducing data from a record medium in which data has been recorded thereon by: sectoring program data in terms of a pre-set data volume as a unit; data-appending copy management information, including copy generation data that specifies the copy generation of program data recorded on the record medium, and copy permitinhibit data that specifies whether or not copying is permitted up to a certain copy generation; error correction coding the sectored program data together with the data-appended copy management information; modulating the error correction coded program data together with the data-appended copy management information; and recording the modulated program data and the modulated data-appended copy management information in a pre-set position in each sector on the record medium, said reproducing apparatus comprising:
reading means for reading the modulated program data and modulated data-appended copy management information from the record medium;
demodulating means for demodulating the modulated program data and modulated data-appended copy management information read from the record medium;
error correction decoding means for error correction decoding the program data together with the data-appended copy management information demodulated in the demodulating step; and
copy controlling means for permitting or prohibiting copying of the error correction decoded program data in accordance with the error correction decoded copy management information,
wherein said sectoring of program data results in at least sectors of a 4-byte synchronization area, a header data area including an error detection code area and said copy management information, a user data area consisting of 2048-byte data, and a second error detection data area consisting of 4-byte data, said second error detection data generated for said header data area and said user data area, and
wherein the data-appending copy management information comprises the copy permitinhibit data that specifies whether or not copying is permitted up to the certain copy generation.
4. The apparatus of claim 3, wherein said data-appended copy management information is located in a header area position of each sector.
5. A reproducing method for reproducing data from a record medium having recorded thereon modulated program data and modulated copy management information, said program data having been error correction coded together with the copy management information, said copy management information specifying the copy generation of said program data recorded on the recorded medium and having been data-converted with the use of address information and ciphering key information, and said program data having been sectorized in terms of a pre-set data volume as a unit, said reproducing method comprising:
reading the modulated program data and data-converted copy management information from the recording medium;
demodulating the read modulated program data and data-converted copy management information;
error correction decoding the demodulated program data together with the demodulated, data-converted copy management information;
deciphering the data-converted copy management information using the address information and the ciphering key information;
desectorizing the program data; and
permitting or prohibiting copying of the program data in accordance with the deciphered copy management information,
wherein said desectorizing of program data uses at least sectors of a 4-byte synchronization area, a header data area including an error detection code area and said copy management information, a user data area consisting of 2048-byte data, and a second error detection data area consisting of 4-byte data.
6. The reproducing method of claim 5 wherein said data-converted copy management information is located in a header area of each sector.
7. The reproducing method of claim 5, wherein said address information corresponds to at least a portion of a respective sector address.
8. An apparatus for reproducing data from a record medium having recorded thereon modulated program data and modulated copy management information, said program data having been error correction coded together with the copy management information, said copy management information specifying the copy generation of said program data recorded on the recorded medium and having been data-converted with the use of address information and ciphering key information, and said program data having been sectorized in terms of a pre-set data volume as a unit, said reproducing apparatus comprising:
reading means for reading the modulated program data and data-converted copy management information from the record medium;
demodulating means for demodulating the read modulated program data and data-converted copy management information;
error correction decoding means for error correction decoding the demodulated program data together with the demodulated, data-converted copy management information;
deciphering means for deciphering the data-converted copy management information using the address information and the ciphering key information;
desectorizing means for desectorizing the program data; and
copy controlling means for permitting or prohibiting copying of the program data in accordance with the deciphered copy management information,
wherein said desectorizing means uses at least sectors of a 4-byte synchronization area, a header data area including an error detection code area and said copy management information, a user data area consisting of 2048-byte data, and a second error detection data area consisting of 4-byte data.
9. The apparatus of claim 8, wherein said data-converted copy management information is located in a header area of each sector.
10. The apparatus of claim 8, wherein said address information corresponds to at least a portion of a respective sector address.