1. A method, comprising:
in a network interface chip:
determining a token count value associated with said network interface chip; and
scheduling based on said token count value, transmission of a packet to be transmitted via said network interface chip, wherein said scheduling comprises suspending said transmission when said token count value meets one or more criteria.
2. The method according to claim 1, wherein said token count value is associated with a specified information flow.
3. The method according to claim 2, wherein said specified information flow is identified based on at least a source address identifier andor destination address identifier associated with said packet.
4. The method according to claim 1, wherein said token count value is associated with a specified class of service.
5. The method according to claim 4, wherein said specified class of service is identified based on a class of service identifier associated with said packet.
6. The method according to claim 1, comprising transmitting said packet at least when said token count value exceeds a minimum value.
7. The method according to claim 1, comprising decreasing said token count value subsequent to transmission of said packet.
8. The method according to claim 1, comprising suspending transmission of said packet when said token count value falls below a minimum value.
9. The method according to claim 1, comprising increasing said token count value based on a determined time rate of increase.
10. The method according to claim 1, comprising determining whether to transmit said packet or suspend transmission of said packet based on a rate control message, wherein said rate control message is received via an interface utilized by said network interface chip for transmitting said packet.
11. A system, comprising:
one or more circuits that are operable to determine a token count value associated with a network interface chip; and
said one or more circuits are operable to schedule based on said token count value transmission of a packet to be transmitted via said network interface chip, wherein said scheduling comprises suspending said transmission when said token count value meets one or more criteria.
12. The system according to claim 11, wherein said token count value is associated with a specified information flow.
13. The system according to claim 12, wherein said specified information flow is identified based on at least a source address identifier andor destination address identifier associated with said packet.
14. The system according to claim 11, wherein said token count value is associated with a specified class of service.
15. The system according to claim 14, wherein said specified class of service is identified based on a class of service identifier associated with said packet.
16. The system according to claim 11, wherein said one or more circuits are operable to enable transmission of said packet at least when said token count value exceeds a minimum value.
17. The system according to claim 11, wherein said one or more circuits are operable to decrease said token count value subsequent to transmission of said packet.
18. The system according to claim 11, wherein said one or more circuits are operable to suspend transmission of said packet when said token count value falls below a minimum value.
19. The system according to claim 11, wherein said one or more circuits are operable to increase of said token count value based on a determined time rate of increase.
20. The system according to claim 11, wherein said one or more circuits are operable to determine whether to transmit said packet or suspend transmission of said packet based on a rate control message, wherein said rate control message is received via an interface utilized by said network interface chip for transmitting said packet.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A current output type DA converter for converting a digital signal into an analog signal, said current output type DA converter comprising:
a control signal input terminal operable to receive a control signal supplied from the outside; and
an output load element having a switching mechanism operable to electrically connect or disconnect said output load element tofrom an analog output node, on the basis of the control signal applied to said control input terminal.
2. A DA converter as defined in claim 1,
wherein said output load element comprises a field effect transistor; and
wherein said field effect transistor electrically connects or disconnects itself tofrom said analog output node on the basis of the control signal inputted to said control input terminal.
3. A DA converter as defined in claim 2, wherein said field effect transistor is a MOS transistor.
4. A DA converter as defined in claim 3,
wherein said MOS transistor is an N channel MOS transistor; and
wherein said N channel MOS transistor has a drain terminal connected to an analog output terminal, a source terminal connected to a ground voltage, and a gate terminal to which the control signal is applied.
5. A semiconductor integrated circuit equipped with a DA converter as defined in claim 4.
6. A DA converter as defined in claim 3,
wherein said MOS transistor is a P channel MOS transistor; and
wherein said P channel MOS transistor has a drain terminal connected to an analog output terminal, a source terminal connected to a power supply voltage, and a gate terminal to which the control signal is applied.
7. A semiconductor integrated circuit equipped with a DA converter as defined in claim 6.
8. A semiconductor integrated circuit equipped with a DA converter as defined in claim 3.
9. A semiconductor integrated circuit equipped with a DA converter as defined in claim 2.
10. A DA converter as defined in claim 1, wherein said switching mechanism included in said output load element electrically disconnects said output load element from said analog output node during normal operation mode while it electrically connects said output load element to said analog output node during wafer-level burn-in mode, on the basis of the control signal inputted to said control input terminal.
11. A semiconductor integrated circuit equipped with a DA converter as defined in claim 10.
12. A DA converter as defined in claim 1,
wherein said output load element comprises a first resistor element and a first switch; and
wherein said first switch electrically connects or disconnects said first resistor element tofrom said analog output node on the basis of the control signal inputted to said control input terminal.
13. A semiconductor integrated circuit equipped with a DA converter as defined in claim 12.
14. A DA converter as defined in claim 1, further comprising:
a resistor element for setting an output current value during the wafer-level burn-in mode; and
a second switch operable to connect or disconnect a reference resistor connected part tofrom said resistor element during the wafer-level burn-in mode;
wherein said second switch electrically connects or disconnects said reference resistor connected part tofrom said resistor element on the basis of the control signal inputted to said control input terminal.
15. A semiconductor integrated circuit equipped with a DA converter as defined in claim 14.
16. A DA converter as defined in claim 1, further comprising:
a reference voltage generation circuit operable to set an output current value during the wafer-level burn-in mode; and
a second switch operable to electrically connect or disconnect a reference voltage application part tofrom said reference voltage generation circuit during the wafer-level burn-in mode;
wherein said second switch electrically connects or disconnects said reference voltage application part tofrom said reference voltage generation circuit on the basis of the control signal inputted to said control input terminal.
17. A semiconductor integrated circuit equipped with a DA converter as defined in claim 16.
18. A semiconductor integrated circuit equipped with a DA converter as defined in claim 1.
19. A DA converter as defined in claim 1, wherein said output load element is not external to said DA converter.