1. A nail dryer includes a housing for contacting a user’s fingers and an air stream generation unit received in the shell for generation of air stream in order to dry nail polish on the user’s nails.
2. The nail dryer according to claim 1 wherein the housing defines at least one vent through which air leaves the housing and a plurality of apertures through which air enters the housing.
3. The nail dryer according to claim 2 wherein the housing includes two shells each defining a plurality of apertures.
4. The nail dryer according to claim 2 wherein the housing includes two shells each defining at least one cutout, wherein the at least one cutout defined in one of the shells matches the at least one cutout defined in the remaining one of the shells so as to make the at least one vent.
5. The nail dryer according to claim 3 wherein one of the shells includes a plurality of hooks formed thereon and the remaining one of the shells defines a corresponding number of recesses for receiving the hooks.
6. The nail dryer according to claim 2 wherein the air stream generation unit includes a motor and a propeller connected with the motor.
7. The nail dryer according to claim 6 wherein the air stream generation unit includes a power supply for powering the motor.
8. The nail dryer according to claim 7 wherein the power supply is a DC power supply received in the housing.
9. The nail dryer according to claim 8 wherein the air stream generation unit includes a circuit for connecting the motor with the DC power supply.
10. The nail dryer according to claim 9 wherein the air stream generation unit includes a switch mounted on the housing.
11. The nail dryer according to claim 6 wherein the housing includes a seat on which the motor is mounted.
12. The nail dryer according to claim 3 wherein the air stream generation unit includes a motor and a propeller connected with the motor.
13. The nail dryer according to claim 12 wherein the seat includes a plurality of plates projecting from one of the shells.
14. The nail dryer according to claim 13 wherein each of the plates of the seat includes an edge complementary to the motor.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A method for forming a damascene interconnection comprising:
forming an insulating layer on a semiconductor substrate;
patterning and etching the insulating layer to form an opening exposing a predetermined region of the semiconductor substrate; and
forming a seed layer covering only a sidewall of the opening and a top surface of the insulating layer,
wherein the seed layer is formed by depositing the seed layer on an entire surface of a resulting structure where the opening is formed, and resputtering the seed layer resident on a bottom of the opening.
2. The method of claim 1, wherein the seed layer is formed using an ionized physical vapor deposition (PVD) apparatus that has a target corresponding to a cathode to which a power for making plasma is applied, and a chuck, positioned opposite to the target, corresponding to an anode to which a radio frequency (RF) bias for accelerating ions is applied.
3. The method of claim 1, wherein the seed layer is made of one selecting from a group consisting of copper, aluminum, and a combination thereof.
4. The method of claim 1, wherein after forming the seed layer, the method further comprising steps of:
forming a copper layer on the seed layer to fill the opening; and
planarly etching the copper layer and the seed layer down to a top surface of the insulating layer.
5. The method of claim 4, wherein the copper layer is formed using an electroplating technique.
6. The method of claim 1, wherein before forming the seed layer, the method further comprising a step of forming a barrier layer on the entire surface of the resulting structure where the opening is formed.
7. The method of claim 6, wherein the barrier layer on the bottom of the opening is selectively removed when the seed layer is formed.
8. The method of claim 6, wherein the barrier layer is made of one selected from a group consisting of Ti, TiN, W, WN, Ta, and TaN.
9. The method of claim 1, wherein the opening comprises a via hole exposing a predetermined region of the substrate, and a groove.
10. A method for forming a damascene interconnection comprising:
forming an insulating layer on a semiconductor substrate;
patterning and etching the insulating layer to form an opening exposing a predetermined region of the semiconductor substrate; and
forming an initial seed layer on an entire surface of a resulting structure where the opening is formed, using an ionized PVD process;
resputtering, in a first step, the initial seed layer on a bottom of the opening to be redeposited on a sidewall of the opening such that the initial seed layer remaining on the bottom of the opening is relatively thinner than that on the sidewall thereof, and
forming, in a second step, an additional seed layer on the entire surface of the resulting structure where the opening is formed.
11. The method of claim 10, wherein the ionized PVD process is performed using an ionized physical vapor deposition (PVD) apparatus that has a target corresponding to a cathode to which a power for making plasma is applied, and a chuck, positioned opposite to the target, corresponding to an anode to which a radio frequency (RF) bias for accelerating ions is applied.
12. The method of claim 11, wherein the power in the second step is higher relative to that in the first step, and the RF bias in the second step is equal to or lower relative to that in the first step.
13. The method of claim 12, wherein the step of resputtering the initial seed layer on the bottom of the opening is performed until the layer underlying the initial seed layer is exposed.
14. The method of claim 10, wherein after forming the additional seed layer, the method further comprising the steps of:
forming a copper layer on the additional seed layer to fill the opening; and
planarly etching the copper layer and the additional seed layer down to a top surface of the insulating layer.
15. A damascene interconnection structure comprising:
a semiconductor substrate;
an opening penetrating the insulating layer to expose a predetermined region of the semiconductor substrate; and
a seed layer formed on a sidewall and a bottom of the opening, and the seed layer on the sidewall of the opening is relatively thicker than that on the bottom thereof.
16. The damascene interconnection structure of claim 15, further comprising a copper layer filling the opening in which the seed layer is formed.
17. The damascene interconnection structure of claim 15, further comprising a barrier layer formed between the sidewall of the opening and the seed layer.
18. The damascene interconnection structure of claim 17, wherein the barrier layer on a bottom of the opening is selectively removed.
19. The damascene interconnection structure of claim 15, wherein the opening is composed of a via hole exposing a predetermined region of the semiconductor substrate, and a groove.