1. A nonvolatile memory device comprising:
a memory cell array having a plurality of nonvolatile memory cells capable of erasing data by applying high voltage;
a control circuit generating an erase execution signal in response to an erase command signal received thereto, the control circuit stopping the erase execution signal and generating a discharge control signal in response to an erase termination signal received thereto, the control circuit stopping the discharge control signal in response to a discharge termination signal received thereto, the control circuit stopping the erase execution signal and the discharge control signal in response to a reset signal received thereto;
a voltage boost circuit providing high voltage to the memory cell for erasing data in response to the erase execution signal;
a timer circuit generating the erase termination signal when a predetermined time elapses after receiving the erase execution signal;
a discharge circuit discharging the high voltage supplied from the voltage boost circuit in response to either one of the discharge control signal and the reset signal received thereto; and
a sensor circuit being enabled in response to either one of the discharge control signal and the reset signal received thereto, the sensor circuit generating the discharge termination signal when the high voltage drops down to a predetermined voltage.
2. A nonvolatile memory device according to claim 1, further comprising a word line decoder for providing the high voltage to the memory cell array.
3. A nonvolatile memory device according to claim 1, wherein the control circuit includes a plurality of flip-flops and a plurality of gate circuits.
4. A nonvolatile memory device according to claim 1, wherein the timer circuit includes an oscillator for generating a clock signal and a counter for counting the clock signal in response to the erase execution signal.
5. A nonvolatile memory device according to claim 1, wherein the control circuit further generating an erase starting signal in response to the reset signal and the erase command signal.
6. A nonvolatile memory device according to claim 5, wherein the wherein the timer circuit includes an oscillator for generating a clock signal in response to the erase starting signal and a counter for counting the clock signal in response to the erase execution signal.
7. A nonvolatile memory device comprising: a memory cell array having a plurality of nonvolatile memory cells capable of erasing data by applying high voltage;
a control circuit generating an erase execution signal in response to an erase command signal received thereto, the control circuit stopping the erase execution signal and generating a discharge control signal in response to an erase termination signal received thereto, the control circuit stopping the discharge control signal in response to a discharge termination signal received thereto, the control circuit stopping the erase execution signal and the discharge control signal in response to a reset signal received thereto;
a pulse circuit generating a pulse signal having a predetermined pulse width in response to the reset signal;
a voltage boost circuit providing high voltage to the memory cell for erasing data in response to the erase execution signal;
a timer circuit generating the erase termination signal when a predetermined time elapses after receiving the erase execution signal;
a discharge circuit discharging the high voltage supplied from the voltage boost circuit in response to either one of the discharge control signal and the reset signal received thereto; and
a sensor circuit being enabled in response to either one of the discharge control signal and the pulse signal received thereto, the sensor circuit generating the discharge termination signal when the high voltage drops down to a predetermined voltage.
8. A nonvolatile memory device according to claim 7, further comprising a word line decoder for providing the high voltage to the memory cell array.
9. A nonvolatile memory device according to claim 7, wherein the control circuit includes a plurality of flip-flops and a plurality of gate circuits.
10. A nonvolatile memory device according to claim 7, wherein the timer circuit includes an oscillator for generating a clock signal and a counter for counting the clock signal in response to the erase execution signal.
11. A nonvolatile memory device according to claim 7, wherein the control circuit further generating an erase starting signal in response to the reset signal and the erase command signal.
12. A nonvolatile memory device according to claim 11, wherein the wherein the timer circuit includes an oscillator for generating a clock signal in response to the erase starting signal and a counter for counting the clock signal in response to the erase execution signal.
13. A nonvolatile memory device comprising:
a memory cell array having a plurality of nonvolatile memory cells capable of erasing data by applying high voltage;
a control circuit generating an erase execution signal in response to an erase command signal received thereto, the control circuit stopping the erase execution signal and generating a discharge control signal in response to either one of a reset signal and an erase termination signal received thereto, the control circuit stopping the erase execution signal and the discharge control signal in response to a discharge termination signal received thereto;
a voltage boost circuit providing high voltage to the memory cell for erasing data in response to the erase execution signal;
a timer circuit generating the erase termination signal when a predetermined time elapses after receiving the erase execution signal;
a discharge circuit discharging the high voltage supplied from the voltage boost circuit in response to the discharge control signal received thereto; and
a sensor circuit being enabled in response to the discharge control signal received thereto, the sensor circuit generating the discharge termination signal when the high voltage drops down to a predetermined voltage.
14. A nonvolatile memory device according to claim 13, further comprising a word line decoder for providing the high voltage to the memory cell array.
15. A nonvolatile memory device according to claim 13, wherein the control circuit includes a plurality of flip-flops and a plurality of gate circuits.
16. A nonvolatile memory device according to claim 13, wherein the timer circuit includes an oscillator for generating a clock signal and a counter for counting the clock signal in response to the erase execution signal.
17. A nonvolatile memory device according to claim 13, wherein the control circuit further generating an erase starting signal in response to the reset signal and the erase command signal.
18. A nonvolatile memory device according to claim 17, wherein the wherein the timer circuit includes an oscillator for generating a clock signal in response to the erase starting signal and a counter for counting the clock signal in response to the erase execution signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A color image processing apparatus for processing color image data expressed by a plurality of colors, comprising:
a drift information storing portion which stores color drift information with respect to each of said plurality of colors;
a boundary detecting portion which detects a boundary portion of the image data of the plurality of colors;
a color change detecting portion which detects a color change in the boundary portion of said image data detected by said boundary detecting portion;
a color drift direction recognizing portion which recognizes a color drift direction with reference to said drift information storing portion on the basis of said color change in said boundary portion detected by said color change detecting portion; and
an image correcting portion which corrects the color change in the boundary portion of said image data on the basis of said color drift direction recognized by said color drift direction recognizing portion.
2. The apparatus according to claim 1, wherein said drift information storing portion stores the presence or absence and a direction of a color drift for another color with respect to each of said plurality of colors.
3. The apparatus according to claim 1, wherein said color change detecting portion detects the color change in the boundary portion on the basis of a concentration difference between adjacent pixels in the boundary portion of said image data.
4. The apparatus according to claim 1, wherein said image correcting portion has:
a discriminating unit which discriminates a white-on-black portion and a color overlap portion on the basis of said color drift direction; and
a color processing unit which executes a color embedding process to said white-on-black portion decided by said discriminating unit and executes a color eliminating process to said color overlap portion.
5. The apparatus according to claim 4, wherein said color processing unit gradually reduces concentration from said boundary portion.
6. The apparatus according to claim 4, wherein said color processing unit allows the color to gradually approach the color of said image data from said boundary portion.
7. The apparatus according to claim 4, wherein said image correcting portion corrects the image data of the color whose concentration is smallest.
8. The apparatus according to claim 4, wherein said image correcting portion corrects the image data having a wider area among the adjacent color image data.