1. A multilayer security element comprising
a first, transparent layer structure having first, translucent sub-regions and
a second, opaque layer structure exhibiting a color-shift effect and having second, transparent sub-regions,
characterized in that
the first layer structure and the second layer structure are stacked on top of one another such that the first, translucent sub-regions of the first layer structure and the second, transparent sub-regions of the second layer structure partially overlap.
2. The security element according to claim 1, characterized in that the first sub-regions exhibit a translucent metallization.
3. The security element according to claim 2, characterized in that the metallization is a contiguous or a screened metal layer.
4. The security element according to claim 1, characterized in that the first sub-regions exhibit diffraction patterns.
5. The security element according to claim 4, characterized in that the diffraction patterns are introduced into an embossing lacquer layer.
6. The security element according to claim 2, characterized in that the translucent metallization is present on the diffraction patterns.
7. The security element according to claim 1, characterized in that the second layer structure is a thin-film structure that comprises an opaque reflector layer and further layers.
8. The security element according to claim 7, characterized in that the reflector layer consists of aluminum.
9. The security element according to claim 7, characterized in that the further layers comprise a dielectric layer and an absorber layer.
10. The security element according to claim 1, characterized in that the second layer structure comprises a layer composed of liquid crystal material, preferably a contiguous layer composed of liquid crystal material, and a dark, preferably black, layer.
11. The security element according to claim 8, characterized in that the second sub-regions are gaps in the reflector layer, preferably in the reflector and absorber layer, or gaps in the dark layer.
12. The security element according to claim 11, characterized in that the gaps are etched, lasered or produced by means of washing processes.
13. The security element according to claim 1, characterized in that the first and second layer structure are present on a substrate having a first and a second substrate surface opposing each other.
14. The security element according to claim 13, characterized in that the first and second layer structure are present on the opposing substrate surfaces of the substrate.
15. The security element according to claim 13, characterized in that the first and second layer structure are present on the same substrate surface of the substrate.
16. The security element according to claim 1, characterized in that the color-shift effect of the second layer structure is perceptible when the security element is viewed from the side of the first layer structure.
17. The security element according to claim 7, characterized in that the further layers of the thin-film structure lie between the opaque reflector layer and the first layer structure, or in that the layer composed of liquid crystal material lies between the dark layer and the first layer structure.
18. The security element according to claim 1, characterized in that the security element is a security thread or a transfer element.
19. A security paper having a window region and, introduced into the paper or applied to the paper, the security element according to claim 1, characterized in that the security element spans the window region.
20. A value document comprising the security paper according to claim 19.
21. A method for manufacturing the security element according to claim 1, in which
a first, transparent layer structure having first, translucent sub-regions and
a second, opaque layer structure exhibiting a color-shift effect and having second, transparent sub-regions are provided,
characterized in that
the first layer structure and the second layer structure are stacked on top of one another such that the first, translucent sub-regions of the first layer structure and the second, transparent sub-regions of the second layer structure partially overlap.
22. The method according to claim 21, in which
a) a substrate having a first and a second substrate surface opposing each other is provided,
b) diffraction patterns are embossed in the substrate, in the first sub-regions on the first surface or the substrate is provided, on the first surface, with a transparent embossing lacquer layer in which diffraction patterns are embossed in the first sub-regions,
c) the embossed sub-regions are provided with a translucent metal layer, and
d) the second layer structure is applied to the second surface.
23. The method according to claim 22, in which, in step d), a layer composed of liquid crystal material is applied to the second surface of the substrate, and thereafter, this layer, except for the second sub-regions, is provided with a dark layer.
24. The method according to claim 22, in which, in step d), the following layers are vapor deposited on the second surface of the substrate in the sequence absorber layer, dielectric layer, reflector layer.
25. The method according to claim 21, in which
a) a substrate having a first and a second substrate surface opposing each other is provided,
b) the second layer structure is applied to the first surface,
c) a transparent embossing lacquer layer in which diffraction patterns are embossed in the first sub-regions is applied to the second layer structure and
d) the embossed sub-regions are provided with a translucent metal layer.
26. The method according to claim 25, in which, in step b), a dark layer is applied to the first surface of the substrate except for the second sub-regions, and a layer composed of liquid material is applied over that.
27. The method according to claim 25, in which, in step b), the following layers are vapor deposited on the first surface of the substrate in the sequence reflector layer, dielectric layer, absorber layer.
28. The method according to claim 21, in which
a) a substrate having a first and a second substrate surface opposing each other is provided,
b) diffraction patterns are embossed in the substrate, in the first sub-regions on the first surface or the substrate is provided, on the first surface, with a transparent embossing lacquer layer in which diffraction patterns are embossed in the first sub-regions,
c) the embossed sub-regions are provided with a translucent metal layer, and
d) the second layer structure is applied thereto.
29. The method according to claim 28, in which, in step d), first a layer composed of liquid material is applied, and a dark layer is applied to that except for the second sub-regions.
30. The method according to claim 28, in which, in step d), the following layers are vapor deposited on the first surface of the substrate in the sequence absorber layer, dielectric layer, reflector layer.
31. The method according to claim 24, wherein the reflector layer is not applied in the second sub-regions, or is subsequently removed.
32. The method according to 31, wherein the reflector layer is removed by means of etching, laser or washing processes.
33. The method according to claim 21, in which a first and a second substrate, each having a first and a second substrate surface opposing each other, are provided, the first layer structure is applied to the first side of the first substrate and the second layer structure to the first side of the second substrate, and the first and second substrates are each laminated together with the respective second surface.
34. The method according to claim 21, characterized in that the security element is cut or punched to produce a security thread or a transfer element.
35. A method for manufacturing a security paper, characterized in that the security element according to claim 1 is introduced into a paper having a window region or is applied to the paper, characterized in that the window region is spanned by the security element.
36. The method according to claim 35, characterized in that the substrate is removed following application of the security element to the paper.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method comprising:
communicating a first voltage to a drive line of a touch sensor;
setting a sense line of the touch sensor to a predetermined voltage;
communicating a second voltage to the drive line, a resulting transition at the drive line from the first voltage to the second voltage causing an amount of charge accumulated on the sense line to be communicated to an integrator;
at the integrator, integrating the amount of charge communicated from the sense line to convert the amount of charge to an output voltage; and
restoring the sense line to the predetermined voltage.
2. The method of claim 1, wherein restoring the sense line to the predetermined voltage comprises communicating current to the sense line through the integrator.
3. The method of claim 1, further comprising selecting the sense line from a plurality of sense lines.
4. The method of claim 1, wherein integrating the amount of charge comprises coupling an integration capacitor of the integrator between a negative terminal and an output terminal of an operational amplifier.
5. The method of claim 1, wherein the predetermined voltage is half of a reference voltage.
6. The method of claim 1, further comprising removing charge from the integrator by bypassing an integration capacitor of the integrator.
7. The method of claim 1, further comprising:
communicating the output voltage to an analog-to-digital converter; and
converting the output voltage to a digital representation.
8. A circuit configured to:
communicate a first voltage to a drive line of a touch sensor;
set a sense line of the touch sensor to a predetermined voltage;
communicate a second voltage to the drive line, a resulting transition at the drive line from the first voltage to the second voltage causing an amount of charge accumulated on the sense line to be communicated to an integrator;
at the integrator, integrate the amount of charge communicated from the sense line to convert the amount of charge to an output voltage; and
restore the sense line to the predetermined voltage.
9. The circuit of claim 8, wherein the circuit is further configured to communicate current to the sense line through the integrator.
10. The circuit of claim 8, wherein the circuit is further configured to select the sense line from a plurality of sense lines.
11. The circuit of claim 8, wherein the circuit is further configured to couple an integration capacitor of the integrator between a negative terminal and an output terminal of an operational amplifier.
12. The circuit of claim 8, wherein the circuit is further configured to remove charge from the integrator by bypassing an integration capacitor of the integrator.
13. The circuit of claim 8, wherein the circuit is further configured to:
communicate the output voltage to an analog-to-digital converter; and
convert the output voltage to a digital representation.
14. An apparatus comprising:
a touch sensor; and
one or more computer-readable non-transitory storage media coupled to the touch sensor that embody logic that is operable when executed to:
communicate a first voltage to a drive line of the touch sensor;
set the sense line of the touch sensor to a predetermined voltage;
communicate a second voltage to the drive line, a resulting transition at the drive line from the first voltage to the second voltage causing an amount of charge accumulated on the sense line to be communicated to an integrator;
at the integrator, integrate the amount of charge communicated from the sense line to convert the amount of charge to an output voltage; and
restore the sense line to the predetermined voltage.
15. The apparatus of claim 14, wherein the logic is further configured to communicate current to the sense line through the integrator.
16. The apparatus of claim 14, wherein the logic is further configured to select the sense line from a plurality of sense lines.
17. The apparatus of claim 14, wherein the logic is further configured to couple an integration capacitor of the integrator between a negative terminal and an output terminal of an operational amplifier.
18. The apparatus of claim 14, wherein the logic is further configured to remove charge from the integrator by bypassing an integration capacitor of the integrator.
19. The apparatus of claim 14, wherein the logic is further configured to:
communicate the output voltage to an analog-to-digital converter; and
convert the output voltage to a digital representation.
20. The apparatus of claim 14, wherein the predetermined voltage is half of a reference voltage.