1. A method for controlling rippling caused by optical proximity correction during an optical lithography process used in manufacturing an integrated circuit, comprising:
selecting a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit;
selecting a second evaluation point for the given segment;
computing a first deviation from a target location for the given segment at the first evaluation point;
computing a second deviation for the given segment at the second evaluation point; and
controlling rippling for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
2. The method of claim 1, wherein the second evaluation point is a supplemental evaluation point.
3. The method of claim 1, wherein both the first evaluation point and the second evaluation point are located on the given segment.
4. The method of claim 1, wherein the first evaluation point is located on the given segment and the second evaluation point is located on an adjacent segment.
5. The method of claim 1, further comprising adjusting the bias, if necessary, for each segment that is part of the layout of the integrated circuit.
6. The method of claim 1, further comprising:
selecting a third evaluation point for the given segment; and
computing a third deviation for the given segment at the third evaluation point;
wherein adjusting the bias for the given segment involves considering the third deviation at the third evaluation point.
7. The method of claim 1, wherein computing the first deviation involves using a model-based technique for computing the first deviation.
8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for controlling rippling caused by optical proximity correction during an optical lithography process used in manufacturing an integrated circuit, the method comprising:
selecting a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit;
selecting a second evaluation point for the given segment;
computing a first deviation from a target location for the given segment at the first evaluation point;
computing a second deviation for the given segment at the second evaluation point; and
controlling rippling for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
9. The computer-readable storage medium of claim 8, wherein the second evaluation point is a supplemental evaluation point.
10. The computer-readable storage medium of claim 8, wherein both the first evaluation point and the second evaluation point are located on the given segment.
11. The computer-readable storage medium of claim 8, wherein the first evaluation point is located on the given segment and the second evaluation point is located on an adjacent segment.
12. The computer-readable storage medium of claim 8, wherein the method further comprises adjusting the bias, if necessary, for each segment that is part of the layout of the integrated circuit.
13. The computer-readable storage medium of claim 8, wherein the method further comprises:
selecting a third evaluation point for the given segment; and
computing a third deviation for the given segment at the third evaluation point;
wherein adjusting the bias for the given segment involves considering the third deviation at the third evaluation point.
14. The computer-readable storage medium of claim 8, wherein computing the first deviation involves using a model-based technique for computing the first deviation.
15. An apparatus for controlling rippling caused by optical proximity correction during an optical lithography process used in manufacturing an integrated circuit, comprising:
a selection mechanism that is configured to,
select a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit, and to
select a second, evaluation point for the given segment;
a deviation computing mechanism that is configured to,
compute a first deviation from a target location for the given segment at the first evaluation point, and to
compute a second deviation for the given segment at the second evaluation point; and
a ripple controlling mechanism that is configured to control ripple for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
16. The apparatus of claim 15, wherein the second evaluation point is a supplemental evaluation point.
17. The apparatus of claim 15, wherein both the first evaluation point and the second evaluation point are located on the given segment.
18. The apparatus of claim 15, wherein the first evaluation point is located on the given segment and the second evaluation point is located on an adjacent segment.
19. The apparatus of claim 15, wherein the bias adjustment mechanism is configured to adjust the bias, if necessary, for each segment that is part of the layout of the integrated circuit.
20. The apparatus of claim 15,
wherein the selection mechanism is additionally configured to select a third evaluation point for the given segment; and
wherein the deviation computing mechanism is additionally configured to compute a third deviation for the given segment at the third evaluation point;
wherein the bias adjustment mechanism is configured to consider the third deviation at the third evaluation point in adjusting the bias for the given segment involves.
21. The apparatus of claim 15, wherein the deviation computing mechanism is configured to compute use a model-based technique in computing the first deviation.
22. A mask to be used in an optical lithography process for manufacturing an integrated circuit, wherein the mask is created through a process that controls rippling caused by optical proximity correction, the process comprising:
selecting a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit;
selecting a second evaluation point for the given segment;
computing a first deviation from a target location for the given segment at the first evaluation point;
computing a second deviation for the given segment at the second evaluation point; and
controlling rippling for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
23. An integrated circuit created through an optical lithography process using a mask, wherein the mask is created through a process that controls rippling caused by optical proximity correction, the process comprising:
selecting a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit;
selecting a second evaluation point for the given segment;
computing a first deviation from a target location for the given segment at the first evaluation point;
computing a second deviation for the given segment at the second evaluation point; and
controlling rippling for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
24. A means for controlling rippling caused by optical proximity correction during an optical lithography process used in manufacturing an integrated circuit, comprising:
a selection means for,
selecting a first evaluation point for a given segment that is part of an edge in a layout of the integrated circuit, and for
selecting a second evaluation point for the given segment;
a deviation computing means for,
computing a first deviation from a target location for the given segment at the first evaluation point, and for
computing a second deviation for the given segment at the second evaluation point; and
a ripple controlling means for controlling ripple for the given segment, if necessary, based upon a measurement of rippling computed from multiple deviations at multiple evaluation points, including the first deviation at the first evaluation point and the second deviation at the second evaluation point, wherein controlling rippling involves breaking the given segments into multiple segments in order to control ripple.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A synchronous sequential access latch array generated by an automated system for generating master-slave latch structures, said latch array comprising:
N2 rows of master-slave pairs wherein N is equal to the number of addresses that are included in said latch array;
an N2 to 1 multiplexer coupled to said N2 rows of master-slave pairs; and
control logic.
2. The latch array of claim 1 wherein said automated system is a logic gate synthesis system that automatically generates master-slave latch structures.
3. The latch array of claim 2 wherein said logic gate synthesis system is invoked from a logic gate synthesis system that generates FIFO structures based on configuration parameter settings.
4. The latch array of claim 1 wherein said control logic is configured to implement data flow to fill latch pairs of respective rows in sequence from row 1 to row N.
5. The latch array of claim 1 wherein said control logic is configured to implement data flow to fill the master latch of respective rows in sequence from row 1 to row N.
6. The latch array of claim 1 wherein said control logic is operable wherein data received by said latch array flows from a master latch in a first half of a clock cycle to a slave latch in a second half of a subsequent clock cycle.
7. The latch array of claim 1 wherein master and slave latches of said latch array comprise random access memory (RAM) addresses.
8. The latch array of claim 1 wherein master and slave latches of said latch array are separately enabled.
9. The latch array of claim 1 providing fully-registered flow control.
10. The latch array of claim 1 being a flow control component of a graphics processing unit (GPU).
11. A method of operating a sequential access memory comprising a master-slave latch pair array, the method comprising:
in a second half of a clock cycle, receiving data into an empty and open master latch in a first row of said master-slave latch pair array, if master-slave latch pairs of other rows are empty or if master-slave latch pairs of other rows are full,
or receiving data into an empty master latch of a subsequent row of said master-slave latch pair array if a master latch and a slave latch of a row or rows preceding said subsequent row are full;
in a first half of a cycle subsequent to a clock cycle in which data is received by a master latch in a row of said master-slave latch pair array, receiving data into a slave latch of said row of said master-slave latch pair array; and
providing access to said data received by said slave latch of said row of said master-slave latch pair array.
12. The method of claim 11 wherein slave latches of said sequential access memory are maintained open and data received by said slave latches flow from master latches of said sequential access memory into said slave latches uninhibited.
13. The method of claim 11 wherein said sequential access memory has N2 rows where N is equal to the number of addresses in said sequential access memory.
14. The method of claim 11 wherein said providing access to said data comprises using an N2:1 multiplexor.
15. The method of claim 11 wherein said sequential access memory provides fully registered flow control.
16. The method of claim 11 wherein said sequential access memory is a FIFO buffer.
17. The method of claim 11 wherein said sequential access memory is a part of a GPU.
18. A method of operating a sequential access memory comprising a master-slave latch pair array, the method comprising:
receiving data into respective master latches in a second half of first respective clock cycles, wherein data that is received in said second half of said first respective clock cycles is allowed to flow uninhibited from respective master latches to respective corresponding slave latches;
receiving data into respective master latches in a second half of second respective clock cycles; and
providing access to data in said respective corresponding slave latches.
19. The method of claim 18 wherein said sequential access memory has N2 rows where N is equal to the number of latches in said sequential access memory.
20. The method of claim 18 said providing access to said data comprises using an N2:1 multiplexor.