1. One or more non-transitory computer readable storage mediums storing one or more sequences of instructions, which when executed by one or more processors, causes
obtaining a associated data of an individual from one or more identities;
extracting information from said associated data to obtain an extracted information;
standardizing said extracted information to obtain a standardized extracted information;
obtaining additional information associated with said one or more identities based on said standardized extracted information;
calculating a confidence level for said additional information, wherein said confidence level is derived based on at least one of (i) a quality, or (ii) an origin of said associated data;
comparing, said additional information with trustworthy information from a database to verify an accuracy of said additional information; and
identifying said individual from said one or more identities and said associated data based on said confidence level and said accuracy.
2. The one or more non-transitory computer readable storage mediums of claim 1, wherein said associated data comprises at least one of (i) one or more posts on a social medium, (ii) data associated with an identity on a social medium, (iii) documents, (iv) emails, or (v) web logs.
3. The one or more non-transitory computer readable storage mediums of claim 1, wherein said standardized extracted information is obtained by at least one of (a) removing one or more noise words from said extracted information, (b) standardizing case associated with said extracted information, or (c) standardizing references associated with said extracted information.
4. The one or more non-transitory computer readable storage mediums of claim 3, wherein said references associated with said information comprise (i) a city names, (ii) statesprovinces, (iii) units of measures, (iv) one or more terms associated with a name.
5. The one or more non-transitory computer readable storage mediums of claim 1, wherein said associated data comprises unstructured data.
6. The one or more non-transitory computer readable storage mediums of claim 1, wherein said extracted information comprises at least one of (i) information associated with a name, (ii) information associated with a location, (iii) information associated with a relationship, (iv) other demographic information, or (v) interaction information.
7. The one or more non-transitory computer readable storage mediums of claim 1, further comprising, assigning a weight for said additional information to derive said confidence level.
8. A entity matching server for identifying an individual from one or more identities and associated data, said entity matching server comprising:
(i) a memory unit that stores (a) a set of modules, and (b) a database, wherein said database comprises an associated data and an extracted information, wherein said extracted information comprises at least one of (i) an information associated with a name, (ii) an information associated with a location, (iii) an information associated with a relationship, (iv) other demographic information, or (v) interaction information; and
(ii) a processor which when configured by said instructions executes said set of modules, wherein said set of modules comprises:
(a) an associated data obtaining module, executed by said processor, that obtains associated data associated with said individual from said one or more identities, wherein said associated data comprises unstructured data;
(b) an information extracting module, executed by said processor, that extracts information from said associated data to obtain an extracted information;
(c) an additional information obtaining module, executed by said processor, that obtains additional information associated with said one or more identities based on said extracted information;
(d) a confidence level identifying module, executed by said processor, that calculates a confidence level for said additional information;
(e) a comparison module, executed by said processor, that compares said additional information with trustworthy information from a database to verify an accuracy of said additional information; and
(f) an individual identification module, executed by said processor, that identifies said individual from said one or more identities and said associated data based on said confidence level and said accuracy.
9. The entity matching server of claim 8, wherein said associated data comprises at least one of (i) one or more posts from a social medium, (ii) data associated with an identity on a social medium, (iii) documents, (iv) emails, or (v) web logs.
10. The entity matching server of claim 8, wherein said set of modules further comprises an extracted information standardizing module, executed by said processor, that standardizes said extracted information to obtain a standardized extracted information.
11. The entity matching server of claim 10, wherein said standardized extracted information is obtained by at least one of (i) removing one or more noise words from said information, (ii) standardizing case associated with said extracted information, or (iii) standardizing references associated with said extracted information.
12. The entity matching server of claim 11, wherein said references associated with said information comprises (i) city names, (ii) statesprovinces, (iii) units of measures, and (iv) one or more terms associated with a name.
13. The entity matching server of claim 8, wherein said confidence level is derived based on at least one of (i) a quality, or (ii) an origin of said associated data.
14. The entity matching server of claim 8, wherein said set of modules further comprises a weight assigning module, executed by said processor, that assigns a weight for said additional information to derive said confidence level.
15. A processor implemented method of identifying an individual from one or more identities and associated data, said processor implemented method comprising:
obtaining said associated data associated with said individual from said one or more identities, wherein said associated data comprises unstructured data;
extracting information from said associated data to obtain an extracted information, wherein said extracted information comprises at least one of (i) information associated with a name, (ii) information associated with a location, (iii) information associated with a relationship, (iv) other demographic information, or (v) interaction information;
standardizing said extracted information by at least one of (a) removing one or more noise words from said extracted information, (b) standardizing case associated with said extracted information, or (c) standardizing references associated with said extracted information;
obtaining additional information associated with said one or more identities based on said standardized extracted information;
calculating a confidence level for said additional information, wherein said confidence level is derived based on (i) a quality, or (ii) an origin of said associated data;
comparing said additional information with trustworthy information from a database to verify an accuracy of said additional information; and
identifying said individual from said one or more identities and said associated data based on said confidence level and said accuracy.
16. The processor implemented method of claim 15, wherein said associated data comprises at least one of (i) one or more posts on a social medium, (ii) data associated with an identity on a social medium, (iii) emails, or (iv) web logs.
17. The processor implemented method of claim 15, wherein said references associated with said information comprises (i) city names, (ii) statesprovinces, (iii) units of measures, (iv) one or more terms associated with a name.
18. The processor implemented method of claim 15, further comprising, assigning a weight for said additional information to derive said confidence level.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A class AB amplifier comprising:
(a) a differential input stage including first and second input transistors each having a gate coupled to a first input and a third input transistor having a gate coupled to a second input, sources of the first, second, and third input transistors being coupled to a current source, drains of the first, second, and third input transistors being coupled to first, second and third conductors;
(b) a first class AB output stage including a first output transistor having a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and a second output transistor having a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor;
(c) a first split folded cascode stage including
i. first and second cascode transistors each having a gate coupled to a reference signal conductor, the first and second cascode transistors having drains coupled to the first and second gate drive conductors, respectively, and sources coupled to the first and second conductors, respectively,
ii. a first current source transistor coupled between the source of the first cascode transistor and a first reference voltage conductor, and a second current source transistor coupled between the source of the second cascode transistor and the first reference voltage conductor; and
(d) first class AB control circuitry including a first input coupled to receive a signal representative of a current in the first output transistor, a second input coupled to receive a signal representative of a current in the second output transistor, and a first output coupled to the first conductor,
wherein the drains of the first and second cascode transistors present high output impedances to the first and second gate drive conductors resulting in high loop gain and consequently resulting in precise control of a first quiescent bias current in the first and second output transistors.
2. The class AB amplifier of claim 1 including third and forth cascode transistors each having a gate coupled to another reference signal conductor, the third and fourth cascode transistors having drains coupled to the first and second gate drive conductors, respectively, and sources coupled to first and second current source devices, respectively, the conductivity type of the third and fourth cascode transistors being opposite to the conductivity type of the first and second cascode transistors.
3. The class AB amplifier of claim 1 wherein the first class AB control circuitry includes a second output coupled to the second conductor.
4. The class AB amplifier of claim 3 including current mirror circuitry including a first current mirror control transistor, the first and second current source transistors being connected as first and second current mirror output transistors, respectively, gates of the current mirror control transistor and the first and second current source transistors being connected together, a drain of the current mirror control transistor being coupled to the third conductor, drains of the first and second current source transistors being coupled to the first and second conductors, respectively.
5. The class AB amplifier of claim 4 wherein the first, second and third input transistors, and the first output transistor are P-channel transistors.
6. The class AB amplifier of claim 4 wherein the second output transistor, the first and second cascode transistors, the first and second current source transistors, and the first current mirror control transistor are N-channel transistors.
7. The class AB amplifier of claim 4 wherein the first, second and third input transistors, and the first output transistor are P-channel transistors, and wherein the second output transistor, the first and second cascode transistors, the first and second current source transistors, and the first current mirror control transistor are N-channel transistors.
8. The class AB amplifier of claim 3 including a current sensing transistor having a source and gate connected to the source and gate, respectively, of the first output transistor and a drain connected to a drain of a diode-connected transistor having a source connected to the first reference voltage conductor and a gate and a drain connected to the first input of the class AB control circuitry to produce the signal representative of the current in the first output transistor.
9. The class AB amplifier of claim 8 wherein the second input of the first class AB control circuitry is connected to the gate of the second output transistor.
10. The class AB amplifier of claim 9 wherein the first class AB control circuitry includes differential amplifying circuitry including first, second and third source-coupled transistors, a reference current source, and a diode-connected reference voltage transistor having a drain connected to receive a reference current from the reference current source, the first and second inputs of the first class AB control circuitry being connected to gates of the first and second source-coupled transistors, respectively, a gate of the third source-coupled transistor being coupled to a gate of the diode-connected reference voltage transistor, a drain of the third source-coupled transistor being coupled to the first conductor, and drains of the first and second source-coupled transistors being coupled to the first conductor.
11. The class AB amplifier of claim 4 including a fourth input transistor having a source, a gate, and a drain connected to the source, gate, and a drain, respectively, of the third input transistor.
12. The class AB amplifier of claim 11 wherein the reference signal conductor conducts a reference signal produced by a DC reference circuit including a reference current source providing a reference current through a diode-coupled transistor having a source coupled to the first reference voltage conductor.
13. The class AB amplifier of claim 11 wherein the first current mirror circuitry includes a second current mirror control transistor having a drain connected to a reference current source and the gates of the first current source transistor and the first and second current source transistors, and a source connected to the third conductor.
14. The class AB amplifier of claim 3 including
a fourth input transistor having a source and gate connected to the source and gate, respectively, of the third input transistor and a drain connected to a fourth conductor;
a second class AB output stage including a third output transistor having a gate coupled to a third gate drive conductor and a drain coupled to a second output conductor and a fourth output transistor having a gate coupled to a fourth gate drive conductor and a drain coupled to the second output conductor;
a second split folded cascode stage including
i. third and fourth cascode transistors each having a gate coupled to the reference signal conductor, the third and fourth cascode transistors having drains coupled to the third and fourth gate drive conductors, respectively, and sources coupled to the third and fourth conductors, respectively,
ii. a third current source transistor coupled between the source of the third cascode transistor and the first reference voltage conductor, and a fourth current source transistor coupled between the source of the fourth cascode transistor and the first reference voltage conductor; and
second class AB control circuitry including a first input coupled to receive a signal representative of a current in the third output transistor, a second input coupled to receive a signal representative of a current in the fourth output transistor, a first output coupled to the third conductor, and a second output coupled to the fourth conductor,
wherein the drains of the third and fourth cascode transistors present high output impedances to the third and fourth gate drive conductors resulting in high loop gain and consequently resulting in precise control of a quiescent bias current in the third and fourth output transistors.
15. The class AB amplifier of claim 14 wherein the first, second, third and fourth input transistors, and the first and third output transistors are P-channel transistors.
16. The class AB amplifier of claim 14 wherein the second and fourth output transistors, the first, second, third and fourth cascode transistors, the first, second, third and fourth current source transistors, and the first current mirror control transistor are N-channel transistors.
17. The class AB amplifier of claim 14 wherein the first, second, third and fourth input transistors, and the first and third output transistors are P-channel transistors, and wherein the second and fourth output transistors, the first, second, third and fourth cascode transistors, the first, second, third and fourth current source transistors, and the first current mirror control transistor are N-channel transistors.
18. The class AB amplifier of claim 14 including a common mode feedback circuit having a first input connected to the first output conductor, first and second outputs connected to the first and second conductors, respectively, to establish a common mode component on the first output conductor, a second input connected to the second output conductor, and third and fourth outputs connected to the third and fourth conductors, respectively, to establish the common mode component on the second output conductor.
19. A method of accurately controlling quiescent bias current in a class AB output stage of an amplifier, comprising:
(a) providing the first class AB output stage with a pull-up transistor having a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and also providing a pull-down transistor having a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor;
(b) providing a split input transistor circuit structure for a first side of a differential input stage by providing first and second input transistors each having a gate coupled to a first input of the amplifier, and also providing a third input transistor having a gate coupled to a second input of the amplifier;
(c) providing a split folded cascode circuit structure having a common gate configuration by providing first and second gate-coupled cascode transistors having drains coupled to the first and second gate drive conductors, respectively, and coupling sources of the first and second gate-coupled cascode transistors to drains of the first and second input transistors, respectively;
(d) providing a third cascode transistor having a gate connected to the reference signal conductor and coupling a source of the third cascode transistor to a drain of the third input transistor by means of a third conductor; and
(e) sensing current in the pull-up and pull-down transistors, comparing the sensed current with a predetermined reference current to produce an error signal representing a difference between the sensed current and the predetermined reference current, amplifying the error signal to produce an error current signal, and introducing the error current signal into a source of one of the first and second gate-coupled cascode transistors.
20. A method of accurately controlling quiescent bias current in a pull-up transistor and a pull-down transistor of a class AB output stage of an amplifier, comprising:
(a) providing a first class AB output stage including the pull-up transistor with a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and the pull-down transistor with a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor; and
(b) providing substantially equal amounts of differential amplification to both an output of a differential input stage of the amplifier and an output of a class AB control circuit of the amplifier by
i. providing a split input transistor circuit structure for a first side of the differential input stage by providing first and second input transistors each having a gate coupled to a first input of the amplifier, and also providing a third input transistor having a gate coupled to a second input of the amplifier,
ii. providing a split folded cascode circuit structure having a common gate configuration by providing first and second cascode transistors each having a gate coupled to a reference signal conductor, the first and second cascode transistors having drains coupled to the first and second gate drive conductors, respectively,
iii. providing a third cascode transistor having a gate connected to the reference signal conductor and a source coupled to a drain of the third input transistor;
iv. coupling drains of the first, second, and third input transistors to the sources of the first, second and third cascode transistors, and
v. sensing current in the pull-up and pull-down transistors, comparing the sensed current with a predetermined reference current to produce a differential error signal representing a difference between the sensed current and the predetermined reference current, amplifying the differential error signal to produce a differential error current signal, and introducing the differential error current signal into the sources of the first and second cascode transistors.
21. Circuitry for accurately controlling quiescent bias current in a class AB output stage of an amplifier, comprising:
(a) a pull-up transistor in the first class AB output stage having a gate coupled to a first gate drive conductor and a drain coupled to a first output conductor and a pull-down transistor in the first class AB output stage having a gate coupled to a second gate drive conductor and a drain coupled to the first output conductor;
(b) means for providing a split input transistor circuit structure for a first side of a differential input stage including first and second input transistors each having a gate coupled to a first input of the amplifier, and also including a third input transistor having a gate coupled to a second input of the amplifier, sources of the first, second, and third input transistors being coupled to a current source;
(c) means for providing a split folded cascode circuit structure having a common gate configuration including first and second gate-coupled cascode transistors having drains coupled to the first and second gate drive conductors, respectively, sources of the first and second gate-coupled cascode transistors being coupled to drains of the first and second input transistors, respectively;
(d) a third cascode transistor having a gate connected to the reference signal conductor, a source of the third cascode transistor being coupled to a drain of the third input transistor by means of a third conductor; and
(e) means for sensing current in the pull-up and pull-down transistors, means for comparing the sensed current with a predetermined reference current to produce an error signal representing a difference between the sensed current and the predetermined reference current, means for amplifying the error signal to produce an error current signal, and means for introducing the error current signal into a source of one of the first and second gate-coupled cascode transistors.