1. A microplasma current switch comprising:
a plasma discharge space defined by a front substrate and a rear substrate along with barrier ribs partitioning a cell region;
an exposed cathode electrode installed on the front substrate;
an exposed anode electrode installed on the front substrate apart from the exposed cathode electrode; and
a plurality of address electrodes installed on the rear substrate in parallel with each other; and a plurality of sustain electrodes constructing a plurality of sustain electrode pairs, wherein the sustain electrodes are insulated from the address electrodes and cross the address electrodes at right angles;
wherein the exposed anode electrode is connected electrically to the exposed cathode electrode by generating a plasma, and an exposed area of the exposed anode electrode to the plasma is smaller than that of the exposed cathode electrode.
2. The microplasma current switch of claim 1, further comprising an electrical device connected to the exposed cathode electrode; and a power supply unit installed between the electrical device and the exposed anode electrode, wherein the electrical device contributes to a display.
3. The microplasma current switch of claim 2, wherein the electrical device further includes
a cathode layer of the electrical device connected to a cathode of the power supply unit;
an electroluminescent device connected to the cathode layer of the electrical device; and the exposed cathode electrode connected to the electroluminescent device,
wherein the exposed cathode is used as an anode layer of the electrical device.
4. The microplasma current switch of claim 2, wherein the electrical device further includes a cathode layer of the electroluminescent device on the front substrate; an electroluminescent layer on the cathode layer of the electroluminescent device; and an anode layer of the electroluminescent device on the electroluminescent layer, wherein the anode layer of the electroluminescent device is used as the exposed cathode electrode, and the exposed anode electrode is formed on the front substrate apart from the exposed cathode electrode.
5. The microplasma current switch of any one of claims 2 to 4, wherein the electrical device is an organic electroluminescent device.
6. A microplasma current switch comprising:
a plurality of plasma discharge spaces defined by a front substrate and a rear substrate along with a plurality of barrier ribs partitioning a plurality of cell regions;
a plurality of designation means, which have display information, selecting the plasma discharge spaces;
a plurality of exposed cathode electrodes installed on the front substrate of the respective plasma discharge spaces; and
a plurality of exposed anode electrodes installed on the front substrate of the respective plasma discharge spaces apart from the corresponding exposed cathode electrodes,
wherein the exposed anode electrodes are connected electrically to the corresponding exposed cathode electrodes by generating plasmas and exposed areas of the exposed anode electrodes to the plasmas are smaller than those of the exposed cathode electrodes; and
wherein the designation means further include a plurality of address electrodes installed on the rear substrate in parallel with each other; and a plurality of sustain electrodes constructing a plurality of sustain electrode pairs, wherein the sustain electrodes are insulated from the address electrodes and cross the address electrodes at right angles.
7. The microplasma current switch of claim 6, wherein a plurality of electrical devices are installed within the respective cell regions, wherein each of the electrical devices includes a cathode layer of an electroluminescent device on the front substrate; an electroluminescent layer on the cathode layer of the electroluminescent device; and an anode layer of the electroluminescent device on the electroluminescent layer, wherein the anode layer of the electroluminescent device is used as the exposed cathode electrode, and the exposed anode electrodes are formed on the front substrate apart from the corresponding exposed cathode electrodes.
8. A microplasma current switch comprising:
a plasma discharge space defined by a front substrate and a rear substrate along with barrier ribs partitioning a cell region;
a first exposed electrode installed on the front substrate of the plasma discharge space;
an insulating layer installed on the first exposed electrode exposing a portion of the first exposed electrode at a first area;
a second exposed electrode installed on the insulating layer and exposed at a second area; and
a plurality of address electrodes installed on the rear substrate in parallel with each other; and a plurality of sustain electrodes constructing a plurality of sustain electrode pairs, wherein the sustain electrodes are insulated from the address electrodes and cross the address electrodes at right angles;
wherein the second exposed electrode is connected electrically to the first exposed electrode by generating a plasma, and wherein the second exposed electrode is exposed at the second area larger than the first area.
9. The microplasma current switch of claim 8, further comprising an electrical device connected to the first exposed electrode; and a power supply unit installed between the electrical device and the second exposed electrode, wherein the electrical device contributes to a display.
10. The microplasma current switch of claim 9, wherein the electrical device further includes an anode layer of the electrical device connected to an anode of the power supply unit; an electroluminescent device connected to the anode layer of the electrical device; and the first exposed electrode connected to the electroluminescent device, wherein the first exposed electrode is used as a cathode layer of the electrical device.
11. The microplasma current switch of claim 9, wherein the plasma discharge space is defined by assembling a front substrate and a rear substrate along with barrier ribs partitioning a cell region, and the electrical device further includes an anode layer of the electroluminescent device on the front substrate; an electroluminescent layer on the anode layer of the electroluminescent device; a cathode layer of the electroluminescent device on the electroluminescent layer; the insulating layer formed on the anode layer of the electroluminescent device including the electroluminescent layer and the cathode layer of the electroluminescent device so as to expose a portion of the cathode layer of the electroluminescent device at the first area; and the second exposed electrode formed on the insulating layer, wherein the second exposed electrode is exposed at the second area larger than the first area, and the cathode layer of the electroluminescent device is used as the first exposed electrode.
12. The microplasma current switch of claim 9, wherein the plasma discharge space is defined by assembling a front substrate and a rear substrate along with barrier ribs partitioning a cell region, and the electrical device further includes a cathode layer of the electroluminescent device on the front substrate; an electroluminescent layer on the cathode layer of the electroluminescent device; an anode layer of the electroluminescent device on the electroluminescent layer; the insulating layer formed on the cathode layer of the electroluminescent device including the electroluminescent layer and the anode layer of the electroluminescent device so as to expose a portion of the anode layer of the electroluminescent device at the first area; and the second exposed electrode formed on the insulating layer, wherein the second exposed electrode is exposed at the second area smaller than the first area, and the anode layer of the electroluminescent device is used as the first exposed electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. An apparatus for transferring data in an electronic system, comprising:
a DMA engine configured to perform a data transfer operation for transferring said data between a peripheral device and a memory device; and
a processor coupled to said DMA engine for creating a DMA structure in said memory device for subsequent access by said DMA engine, said processor also selectively programming control registers of said DMA engine to thereby facilitate efficiently performing said data transfer operation.
2. The apparatus of claim 1 wherein said data transfer operation includes a direct memory access data transfer operation.
3. The apparatus of claim 1 wherein said memory device is implemented as a synchronous dynamic random-access memory device that is optimized for performing block data transfer operations.
4. The apparatus of claim 1 wherein said electronic system is implemented as one of an audiovisual electronic device, a consumer electronics device, a portable electronics device, and a computer device.
5. The apparatus of claim 1 wherein said electronic system includes a bridge device that facilitates bi-directional communications between said processor, said peripheral device, and said memory device.
6. The apparatus of claim 5 wherein said bridge device includes a processor interface for communicating with said processor, a memory interface for communicating with said memory device, a peripheral interface for communicating with said peripheral device.
7. The apparatus of claim 1 wherein said peripheral device is implemented as one of an integrated circuit device and an electronic system.
8. The apparatus of claim 1 wherein said DMA structure includes at least one command structure that has command information for performing said data transfer operation.
9. The apparatus of claim 8 wherein said command structure includes a starting source address, a starting destination address, a transfer-bytes total field, a next command-structure pointer, a last command-structure field, an interruptno interrupt after current transfer field, and a transfer-info field.
10. The apparatus of claim 1 wherein said DMA structure includes a series of command structures that are linked together in a linked list to thereby perform a series of direct memory access operations.
11. The apparatus of claim 1 wherein said DMA engine includes a state machine for controlling said data transfer operation, one or more command registers for locally storing one or more command structures from said DMA structure, and said control registers.
12. The apparatus of claim 1 wherein said control registers include a DMA start register that said processor may program to start said data transfer operation, a DMA haltresume register that said processor may program to halt or resume said data transfer operation, a DMA clear interrupt register that said processor may program to clear an interrupt of said data transfer operation, a DMA link list address register that said processor may program with a physical address in said memory device of a first command structure in said DMA structure, and a DMA status register that said DMA engine may program to indicate a current status of said data transfer operation.
13. The apparatus of claim 1 wherein said processor initially creates said DMA structure in said memory device, said DMA structure including one or more command structures that each include command information for performing a separate DMA data transfer operation, said memory device being optimized to perform block data transfers.
14. The apparatus of claim 13 wherein said processor programs said control registers with DMA data transfer information that is then locally available to said DMA engine for performing said data transfer operation.
15. The apparatus of claim 14 wherein said processor instructs said DMA engine to perform said data transfer operation after programming said control registers, said processor then releasing control of said data transfer operation and performing other system processing tasks for said electronic system.
16. The apparatus of claim 15 wherein said DMA engine copies one or more designated command structures from said DMA structure in said memory device into one or more command registers that are locally coupled to said DMA engine.
17. The apparatus of claim 16 wherein said DMA engine performs said data transfer operation between said peripheral device and said memory device by referring to said control registers and said command registers.
18. The apparatus of claim 17 wherein said DMA engine detects a stop condition while performing said data transfer operation.
19. The apparatus of claim 18 wherein said DMA engine stops said data transfer operation and notifies said processor regarding said stop condition.
20. The apparatus of claim 17 wherein said DMA engine transfers a new linked command structure from said DMA structure into said command registers for performing a linked DMA data transfer operation without an intervention by said processor.
21. A method for transferring data in an electronic system, comprising the steps of:
creating a DMA structure in a memory device for subsequent access by a DMA engine;
programming control registers of said DMA engine with a processor to thereby facilitate efficiently performing a data transfer operation; and
performing said data transfer operation by utilizing said DMA engine to thereby transfer said data between a peripheral device and said memory device.
22. The method of claim 21 wherein said data transfer operation includes a direct memory access data transfer operation.
23. The method of claim 21 wherein said memory device is implemented as a synchronous dynamic random-access memory device that is optimized for performing block data transfer operations.
24. The method of claim 21 wherein said electronic system is implemented as one of an audiovisual electronic device, a consumer electronics device, a portable electronics device, and a computer device.
25. The method of claim 21 wherein said electronic system includes a bridge device that facilitates bi-directional communications between said processor, said peripheral device, and said memory device.
26. The method of claim 25 wherein said bridge device includes a processor interface for communicating with said processor, a memory interface for communicating with said memory device, a peripheral interface for communicating with said peripheral device.
27. The method of claim 21 wherein said peripheral device is implemented as one of an integrated circuit device and an electronic system.
28. The method of claim 21 wherein said DMA structure includes at least one command structure that has command information for performing said data transfer operation.
29. The method of claim 28 wherein said command structure includes a starting source address, a starting destination address, a transfer-bytes total field, a next command-structure pointer, a last command-structure field, an interruptno interrupt after current transfer field, and a transfer-info field.
30. The method of claim 21 wherein said DMA structure includes a series of command structures that are linked together in a linked list to thereby perform a series of direct memory access operations.
31. The method of claim 21 wherein said DMA engine includes a state machine for controlling said data transfer operation, one or more command registers for locally storing one or more command structures from said DMA structure, and said control registers.
32. The method of claim 21 wherein said control registers include a DMA start register that said processor may program to start said data transfer operation, a DMA haltresume register that said processor may program to halt or resume said data transfer operation, a DMA clear interrupt register that said processor may program to clear an interrupt of said data transfer operation, a DMA link list address register that said processor may program with a physical address in said memory device of a first command structure in said DMA structure, and a DMA status register that said DMA engine may program to indicate a current status of said data transfer operation.
33. The method of claim 21 wherein said processor initially creates said DMA structure in said memory device, said DMA structure including one or more command structures that each include command information for performing a separate DMA data transfer operation, said memory device being optimized to perform block data transfers.
34. The method of claim 33 wherein said processor programs said control registers with DMA data transfer information that is then locally available to said DMA engine for performing said data transfer operation.
35. The method of claim 34 wherein said processor instructs said DMA engine to perform said data transfer operation after programming said control registers, said processor then releasing control of said data transfer operation and performing other system processing tasks for said electronic system.
36. The method of claim 35 wherein said DMA engine copies one or more designated command structures from said DMA structure in said memory device into one or more command registers that are locally coupled to said DMA engine.
37. The method of claim 36 wherein said DMA engine performs said data transfer operation between said peripheral device and said memory device by referring to said control registers and said command registers.
38. The method of claim 37 wherein said DMA engine detects a stop condition while performing said data transfer operation.
39. The method of claim 38 wherein said DMA engine stops said data transfer operation and notifies said processor regarding said stop condition.
40. The method of claim 37 wherein said DMA engine transfers a new linked command structure from said DMA structure into said command registers for performing a linked DMA data transfer operation without an intervention by said processor.
41. The method of claim 21 wherein said processor selectively programs said control registers of said DMA engine to provide locally-accessible transfer information and thereby avoid a block transfer penalty associated with repeatedly accessing relatively small amounts of DMA transfer information from said memory device, said processor creating said DMA structure in said memory device to thereby provide an effective storage medium for storing a linked list of multiple command structures.
42. An apparatus for transferring data in an electronic system, comprising:
means for creating a DMA structure in a memory device for subsequent access by a DMA engine;
means for programming control registers of said DMA engine to thereby facilitate efficiently performing a data transfer operation; and
means for performing said data transfer operation to thereby transfer said data between a peripheral device and said memory device.
43. A method for performing a DMA data transfer procedure in an electronic system, comprising the steps of:
creating a DMA structure in a block transfer memory by utilizing a central processing unit, said DMA structure including a linked-list of command structures that each include command information for performing said DMA data transfer procedure;
programming one or more local control registers of a DMA engine with said central processing unit in response to a DMA data transfer requirement, said local control registers including a DMA start register and at least one of a DMA haltresume register, a DMA clear interrupt register, a DMA link list address register, and a DMA status register;
copying at least one of said command structures from said block transfer memory into one or more local command registers that are coupled to said DMA engine;
performing said DMA data transfer operation with said DMA engine by referencing said local control registers and said local command registers;
detecting a stop condition corresponding to said DMA data transfer operation;
stopping said DMA data transfer operation by utilizing said DMA engine; and
notifying said central processing unit regarding said stop condition of said DMA data transfer operation.