1. A pair of pMOS transistors, comprising:
a first SiGe channel region on a first region of a silicon substrate, the first SiGe channel region having a first concentration of Ge;
a second SiGe channel region on a second region of the silicon substrate, the second SiGe channel region having a second concentration of Ge, different than the first concentration of Ge;
a gate insulator on the first and second SiGe channel regions;
a first gate electrode on the gate insulator over the first SiGe channel region;
a second gate electrode on the gate insulator over the second SiGe channel region, wherein the first gate electrode and the second gate electrode have a same mid-gap work function to provide a first of the pair of pMOS transistors with a threshold voltage that is different than a second of the pair of pMOS transistors; and
a p-type doped source and drain on opposite sides of both the first and second gate electrodes.
2. The pMOS transistors of claim 1, wherein the first and second SiGe channel regions are substantially free of dopant species.
3. The pMOS transistors of claim 1, wherein the first SiGe channel region further comprises a first cladding layer comprising the first germanium concentration on a first non-planar silicon body, and wherein the second SiGe channel region further comprises a second cladding layer comprising the second germanium concentration on a second non-planar silicon body, the first and second non-planar silicon bodies having a pair of opposite sidewalls separated by a distance defining a semiconductor body width.
4. The pMOS transistors of claim 3, wherein the gate insulator is formed on the sidewalls and on a top surface of the first and second cladding layers.
5. The pMOS transistors of claim 3, wherein the first and second cladding layer further comprise an epitaxial SiGe layer on the first and second non-planar silicon bodies.
6. The pMOS transistors of claim 5, wherein at least one of the first and second cladding layers have a thickness of between 5 \u212b and 300 \u212b and wherein at least one of the first or second concentration of Ge is between 25% and 30%.
7. The pMOS transistors of claim 1, wherein the first gate electrode and the second gate electrode further comprise a same material having a mid-gap work function between 4.5 and 4.9 eV.
8. The pMOS transistors of claim 7, wherein the first gate electrode and the second gate electrode further comprises a titanium nitride layer disposed on the gate insulator.
9. The pMOS transistors of claim 1, wherein the threshold voltage between the pair of pMOS transistors is differs by at least 150 mV.
10. The pMOS transistors of claim 1, wherein the gate insulator is a metal oxide dielectric layer.
11. A CMOS device, comprising
the pMOS transistors of claim 1, and
an nMOS transistor including a gate electrode of a material having a mid-gap work function between 4.5 and 4.9 eV.
12. The semiconductor device of claim 11, wherein the gate electrode comprises titanium nitride.
13. The semiconductor device of claim 11, wherein the nMOS transistor channel comprises monocrystalline silicon.
14. The semiconductor device of claim 11, wherein the nMOS transistor channel is undoped.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage apparatus comprising:
a plurality of terminals including a reset terminal, a clock terminal, a power supply terminal and a ground terminal, the reset terminal being configured to be connected to a host side reset terminal to which a reset signal is supplied from a host device, the clock terminal being configured to be connected to a host side clock terminal to which a system clock is supplied from the host device, the power supply terminal being configured to be connected to a host side power supply terminal to which a power supply voltage is supplied from the host device, the ground terminal being configured to be connected to a host side ground terminal to which ground voltage is supplied from the host device;
a nonvolatile storage section, and
a control section that controls the nonvolatile storage section,
wherein the control section comprises:
a detection circuit that detects a floating state in at least one of the power supply terminal and the ground terminal, the detection circuit being configured to output a detection signal indicating whether the floating state is detected or not; and
a mask process circuit that performs a mask process of a system clock that is used to control the nonvolatile storage section,
wherein the mask process circuit inputs the detection signal, and masks the system clock when the floating state is detected by the detection circuit.
2. The storage apparatus according to claim 1, wherein
the mask process section has a holding section which maintains a logic level of the detection signal.
3. The storage apparatus according to claim 2, wherein the holding section clears the holding state of the logic level of the detection signal when a reset signal which resets the control section becomes active.
4. The storage apparatus according to claim 1, wherein the control section has an access control section that performs access control of reading or writing to the nonvolatile storage section, and
the mask process section masks the system clock which is supplied to the access control section when the floating state is detected by the detection circuit.
5. The storage apparatus according to claim 4, wherein
the control section has a transmission section that performs data transmission to the host device,
the mask process section does not mask the system clock which is supplied to the transmission section and the access control section such that the access control section reads data from the nonvolatile storage section and the transmission section transmits the data to the host device, when the floating state is not detected by the detection circuit, and
the mask process section masks the system clock, such that the data is not transmitted to the host device, and the detection of the floating state is detected as a communication error by the host device, when the floating state is detected by the detection circuit.
6. The storage apparatus according to claim 1, wherein
the control section has a data determination section determining that data received from the host device is normal or not, and
the mask process section masks the system clock which is supplied to the data determination section, when the floating state is detected by the detection circuit.
7. The storage apparatus according to claim 6, wherein the control section has a transmission section that performs data transmission to the host device,
the mask process section does not mask the system clock such that the data determination section determines whether data received from the host device is normal or not, and the transmission section transmits information on the determination results to the host device by the data determination section, when the floating state is not detected by the detection circuit, and
the mask process section masks the system lock such that the information on the determination result is not transmitted to the host device, and the detection of the floating state is detected as a communication error by the host device, when the floating state is detected by the detection circuit.
8. The storage apparatus according to claim 1, wherein the nonvolatile storage section is a nonvolatile memory that is necessary for rewriting of the read data in the reading operation.
9. A system comprising:
a storage apparatus according to claim 1; and
a host device.
10. A liquid container comprising:
an ink chamber configured to contain ink;
a plurality of terminals including a clock terminal, a reset terminal and a power supply terminal, the clock terminal being configured to be connected to a host side clock terminal to which a system clock is supplied from a host device, the reset terminal being configured to be connected to a host side reset terminal to which a reset signal is supplied from the host device, the power supply terminal being configured to be connected to a host side power supply terminal to which a power supply voltage is supplied from the host device;
a nonvolatile storage section configured to be controlled by the system clock;
a control section that controls the nonvolatile storage section, the control section including a detection circuit that detects a floating state in the power supply terminal, the detection circuit being configured to compare a voltage of the reset signal with the power supply voltage and to output a detection signal indicating whether the floating state is detected or not; and
a mask process circuit that performs a mask process of the system clock, the mask process circuit being configured to input the detection signal and mask the system clock when the floating state is detected by the detection circuit.
11. A liquid container according to claim 10, the detection circuit being configured to compare a voltage of the reset signal with the power supply voltage and to output a detection signal indicating whether the floating state is detected or not.
12. A liquid container according to claim 11, the detection circuit having a differential pair that is configured to compare the voltage of the reset signal with the power supply voltage, the reset signal being input to a first terminal of the differential pair, the power supply voltage being input to a second terminal of the differential pair.
13. A liquid container comprising:
an ink chamber configured to contain ink;
a plurality of terminals including a clock terminal and a ground terminal, the clock terminal being configured to be connected to a host side clock terminal to which a system clock is supplied from a host device, the ground terminal being configured to be connected to a host side ground terminal to which ground voltage is supplied from the host device;
a nonvolatile storage section configured to be controlled by the system clock;
a control section that controls the nonvolatile storage section, the control section including a detection circuit that detects a floating state in the ground terminal, the detection circuit being configured to compare a voltage of the system clock with the ground voltage and to output a detection signal indicating whether the floating state is detected or not; and
a mask process circuit that performs a mask process of the system clock, the mask process circuit being configured to input the detection signal and mask the system clock when the floating state is detected by the detection circuit.
14. A liquid container according to claim 13, the detection circuit being configured to compare a voltage of the system clock with the ground voltage and to output a detection signal indicating whether the floating state is detected or not.
15. A liquid container according to claim 14, the detection circuit having a differential pair that is configured to compare a voltage of the system clock with the ground voltage, the system clock being input to a first terminal of the differential pair, the ground voltage being input to a second terminal of the differential pair.