1. A method of enabling input into a handheld electronic device, wherein the handheld electronic device comprises one or more processors and one or more memory devices, the method comprising:
storing a core alphabet in a static portion of the one or more memory devices;
storing an extended alphabet in a modifiable portion of the one or more memory devices;
detecting a first set of input-key selections;
producing for selection a prefix object based on the first set of input-key selections, wherein the prefix object comprises at least one character from the extended alphabet;
detecting an additional input-key selection; and
producing for selection an artificial variant comprising the prefix object followed by an additional character, wherein the additional character is selected by seeking a character from the core alphabet based on the additional input-key selection.
2. The method of claim 1, wherein the at least one character from the extended alphabet is a diacritical character.
3. The method of claim 1, wherein a corresponding word object does not exist for the artificial variant.
4. The method of claim 1, wherein the additional character is selected from a set of characters in the core alphabet assigned to a key corresponding to the additional input-key selection.
5. The method of claim 4, wherein a character in the extended alphabet is also assigned to the key corresponding to the additional input-key selection.
6. A handheld electronic device comprising:
a display
a processor apparatus comprising one or more processors and one or more memory devices, the one or more memory devices having stored instructions which, when executed on the one or more processors, cause the handheld electronic device to perform operations comprising:
storing a core alphabet in a static portion of the one or more memory devices;
storing an extended alphabet in a modifiable portion of the one or more memory devices;
detecting a first set of input-key selections;
producing for selection a prefix object based on the first set of input-key selections, wherein the prefix object comprises at least one character from the extended alphabet;
detecting an additional input-key selection; and
producing for selection an artificial variant comprising the prefix object followed by an additional character, wherein the additional character is selected by seeking a character from the core alphabet based on the additional input-key selection.
7. The handheld electronic device of claim 6, wherein the at least one character from the extended alphabet is a diacritical character.
8. The handheld electronic device of claim 6, wherein a corresponding word object does not exist for the artificial variant.
9. The handheld electronic device of claim 6, wherein the additional character is selected from a set of characters in the core alphabet assigned to a key corresponding to the additional input-key selection.
10. The handheld electronic device of claim 9, wherein a character in the extended alphabet is also assigned to the key corresponding to the additional input-key selection.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor memory device comprising:
a group of address pads; and
an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.
2. The semiconductor memory device of claim 1, wherein the first and second addresses constitute either one of row and column addresses for selecting memory cells.
3. The semiconductor memory device of claim 1, wherein the first transition is a high-low transition of the external clock signal and the second transition is a low-high transition of the external clock signal.
4. The semiconductor memory device of claim 1, further comprising an internal clock generator circuit for generating a first internal clock signal at the first transition of the external clock signal and a second internal clock signal at the second transition of the external clock signal.
5. The semiconductor memory device of claim 4, wherein the input circuit receives the first address from the address pads in response to the first internal clock signal during a test mode of operation.
6. The semiconductor memory device of claim 4, wherein the input circuit receives the second address from the address pads in response to the second internal clock signal during test and normal modes of operation.
7. The semiconductor memory device of claim 6, further comprising another group of address pads.
8. The semiconductor memory device of claim 7, wherein the input circuit receives the first address from the other group of address pads in response to the first internal clock signal during a normal mode of operation.
9. The semiconductor memory device of claim 4, wherein the input circuit comprises:
a first switch part for receiving the first address from the one group of address pads in response to the first internal clock signal during a test mode of operation; and
a second switch part for receiving the second address from the one group of address pads in response to the second internal clock signal during test and normal modes of operation.
10. The semiconductor memory device of claim 7, wherein the input circuit comprises:
a first switch part for receiving the first address from the one group of address pads in response to the first internal clock signal during a test mode of operation; and
a second switch part for receiving the second address from the one group of address pads in response to the second internal clock signal during test and normal modes of operation,
wherein the first switch part receives the first address from the other group of address pads in response to the second internal address during a normal mode of operation.
11. A semiconductor memory device comprising:
a plurality of address pads for receiving external address signals;
an internal clock generator circuit configured to generate a first internal clock signal a second internal clock signal at both edges of an external clock signal, respectively;
a first switch circuit configured to receive first address signals from a part of the address pads in response to the first internal clock signal; and
a second switch circuit configured to receive second address signals from the part of the address pads in response to the second internal clock signal.
12. The semiconductor memory device of claim 11, wherein the first and second address signals constitute either one of row and column addresses for selecting memory cells.
13. The semiconductor memory device of claim 11, wherein the first switch circuit receives the first address signals in response to the first internal clock signal during a test mode of operation.
14. The semiconductor memory device of claim 11, wherein the second switch circuit receives the second address signals in response to the second internal clock signals during test and normal modes of operation.
15. The semiconductor memory device of claim 13, wherein the first switch circuit receives the first address signals from the other of the address pads in response to the second clock signal during a normal mode of operation.
16. The semiconductor memory device of claim 11, wherein the first switch circuit receives the first address signals before an external command is received, during a test mode of operation.
17. The semiconductor memory device of claim 16, wherein the external command is one selected from a group of an active command, a read command, and a write command.