1. A motion guide device, comprising:
a track member having a ball rolling surface extending in a longitudinal direction thereof;
a moving member main body having a load ball rolling surface that is opposed to the ball rolling surface to form a load ball path, and a ball return path provided in parallel to the load ball path;
a lid member having a direction changing path that connects the load ball path and the ball return path to each other, the lid member being fixed to an end portion of the moving member main body in a moving direction thereof; and
a plurality of balls arranged in an endless circulation path including the load ball path, the ball return path, and the direction changing path,
wherein the lid member comprises an introducing portion at an entrance region of the direction changing path that is connected to the load ball path,
wherein the introducing portion comprises:
a first contact surface that is provided adjacent to one side portion of the ball rolling surface and continuous with the direction changing path so as to intersect with the load ball path, the first contact surface guiding the plurality of balls rolling on the ball rolling surface to another side portion of the ball rolling surface; and
a second contact surface located on an opposite side to the first contact surface across the ball rolling surface, and
wherein the plurality of balls are guided by the first contact surface so as to be transferred from the ball rolling surface of the track member onto the second contact surface.
2. The motion guide device according to claim 1,
wherein the introducing portion further comprises an entrance wall portion formed between the first contact surface and the second contact surface along a direction in which the plurality of balls roll, the entrance wall portion overlapping with the ball rolling surface of the track member, and
wherein the plurality of balls rolling on the ball rolling surface abut against the first contact surface without coming into contact with a leading edge of the entrance wall portion.
3. The motion guide device according to claim 2,
wherein the lid member comprises:
a lid member main body having an outer peripheral guide curved surface of the direction changing path formed therein; and
an inner peripheral member to be fitted to the lid member main body, the inner peripheral member having an inner peripheral guide surface of the direction changing path, and
wherein the first contact surface is provided in the lid member main body, and the second contact surface is provided in the inner peripheral member.
4. The motion guide device according to claim 3, wherein the plurality of balls are guided at the introducing portion in a direction different from a direction in which a load acts on the plurality of balls in the load ball path.
5. The motion guide device according to claim 4, wherein the second contact surface has an end edge that faces the track member and is located on a tangent line of an edge of the ball rolling surface of the track member.
6. The motion guide device according to claim 3, wherein the second contact surface has an end edge that faces the track member and is located on a tangent line of an edge of the ball rolling surface of the track member.
7. The motion guide device according to claim 2,
wherein the lid member comprises:
a lid member main body having an outer peripheral guide curved surface of the direction changing path formed therein; and
an inner peripheral member to be fitted to the lid member main body, the inner peripheral member having an inner peripheral guide surface of the direction changing path, and
wherein the first contact surface and the second contact surface are provided in the lid member main body.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit, comprising:
a. a first transistor and a second transistor cascaded between protected node and ground
b. a first circuit coupled to a voltage bus and to the gate of a first transistor; and
c. a second circuit coupled to ground and to the gate of the second transistor.
2. The circuit of claim 1, wherein the first circuit comprising a metal-oxide semiconductor (MOS) transistor.
3. The circuit of claim 1, where in the second circuit further couple to the gate of the transistor of the first circuit.
4. The circuit of claim 1, wherein the second circuit is further coupled to the voltage bus.
5. The circuit of claim 2, wherein the MOS transistor of the first circuit is a PMOS transistor.
6. The circuit of claim 5, wherein the source of the PMOS transistor is coupled to the voltage bus, the drain of the PMOS transistor is coupled to the gate of the first transistor, the gate of the PMOS transistor is coupled to the second circuit, and the well of the PMOS transistor is coupled to a floating N-well.
7. The circuit of claim 1, wherein the second circuit further comprises:
a. an NMOS transistor coupled to the first circuit and to ground; and,
b. a resistor coupled to the voltage bus and to the gate of the NMOS transistor.
8. The circuit of claim 7, wherein the source of the NMOS transistor is coupled to ground, the gate of the NMOS transistor is coupled to the voltage bus, and the drain of the NMOS transistor is coupled to the first circuit.
9. The circuit of claim 8, wherein:
a. the first circuit further comprises a PMOS transistor; and
b. the drain of the NMOS transistor is coupled to the gate of the PMOS transistor.
10. The circuit of claim 7, wherein the bulk of the NMOS transistor is coupled to a substrate bus adapted to provide a substrate voltage.
11. The circuit of claim 1, wherein the second circuit further comprises:
a. a NMOS transistor coupled to the first circuit and to ground; and
b. a PMOS transistor coupled to the voltage bus and to the gate of the NMOS transistor.
12. The circuit of claim 11, wherein the source of the PMOS transistor is coupled to the voltage bus, the gate of the PMOS transistor is coupled to the drain of the PMOS transistor, and the drain of the PMOS transistor is coupled to the gate of the NMOS transistor.
13. The circuit of claim 7, wherein the first circuit is applied to a gate of first cascaded NMOS transistor.
14. The circuit of claim 7, wherein the second circuit is applied to a gate of second cascaded NMOS transistor.
15. The circuit of claim 14, wherein:
a. the first transistor is coupled to an inputoutput (IO) bus; and
b. the IO bus is coupled to an IO pad.
16. The circuit of claim 15, wherein the second transistor is coupled to ground and the gate of NMOS transistor.
17. A circuit for providing electro-static discharge (ESD) protection for a semiconductor circuit having two fingers, a voltage bus, two cascaded transistor sets between an IO pad and a ground voltage, each transistor set having a first transistor, the improvement comprising a gate coupling circuit between the first transistors of each of the two cascaded transistor sets.
18. The circuit of claim 17, wherein the gate coupling circuit comprises:
a first circuit coupled to the voltage bus and to a gate of the first transistor of one of the cascaded transistor sets, the first circuit comprising a metal-oxide semiconductor (MOS) transistor; and,
a second circuit coupled to the ground voltage and to a gate of the transistor of the first circuit.
19. The circuit of claim 17, wherein the gate coupling circuit is adapted such that the body effect in an ESD event maintains a voltage on the gates of the first transistors.
20. The circuit of claim 17, wherein the transistors in each of the cascaded transistor sets is a NMOS transistor.
21. In a circuit for providing high voltage tolerant electro-static discharge (ESD) protection for a semiconductor circuit having a plurality of fingers, a voltage bus, a plurality of cascaded transistor sets between an IO pad and a ground voltage, each transistor set having a first transistor and a second transistor, a method for uniformly turning on each of the plurality of fingers during a ESD event comprising; coupling the gates of the first transistors of each of the plurality cascaded transistor sets with a gate coupling circuit.