1. An integrated circuit, comprising:
an array of memory cells;
volatile storage;
non-volatile storage; and
a circuit configured to sense first addresses of first defective memory cells from the non-volatile storage to obtain sensed first addresses, wherein the circuit detects second defective memory cells via the sensed first addresses and stores second addresses of the second defective memory cells in the volatile storage and the non-volatile storage.
2. The integrated circuit of claim 1, wherein the first addresses are stored in first entries in the volatile storage and the second addresses are stored in second entries in the volatile storage, which are different than the first entries in the volatile storage.
3. The integrated circuit of claim 2, wherein the sensed first addresses are stored in the first entries in the volatile storage.
4. The integrated circuit of claim 2, wherein the first entries are grayed out prior to storing the second addresses in the non-volatile storage.
5. The integrated circuit of claim 2, wherein the first addresses are stored in third entries in the non-volatile storage and the second addresses are stored in fourth entries in the non-volatile storage, which are different than the third entries in the non-volatile storage.
6. The integrated circuit of claim 5, wherein the first entries correspond to the third entries and the second entries correspond to the fourth entries.
7. The integrated circuit of claim 5, wherein the second addresses are stored in the non-volatile storage via the volatile storage and the second entries correspond to the fourth entries.
8. The integrated circuit of claim 1, wherein the array of memory cells includes banks of memory cells and the volatile storage includes sets of volatile storage elements and each of the banks of memory cells is electrically coupled to a different one of the sets of volatile storage elements.
9. The integrated circuit of claim 8, wherein the non-volatile storage includes sets of non-volatile storage elements and each of the sets of non-volatile storage elements corresponds to a different one of the banks of memory cells.
10. The integrated circuit of claim 8, wherein the circuit provides a repair status flag that indicates one of the sets of volatile storage elements is full.
11. A memory device, comprising:
an array of memory cells;
volatile storage;
non-volatile storage; and
a circuit configured to detect first defective memory cells and store first addresses of the first defective memory cells in the volatile storage and the non-volatile storage, wherein the circuit senses the first addresses stored in the non-volatile storage to obtain sensed first addresses, detects second defective memory cells via the sensed first addresses and stores second addresses of the second defective memory cells in the volatile storage and the non-volatile storage.
12. The memory device of claim 11, wherein the first addresses are stored in first entries in the volatile storage and the second addresses are stored in second entries in the volatile storage, which are different than the first entries in the volatile storage.
13. The memory device of claim 12, wherein the first entries are grayed out prior to programming the second addresses into the non-volatile storage via the volatile storage.
14. The memory device of claim 12, wherein the sensed first addresses are stored in the first entries in the volatile storage.
15. An integrated circuit, comprising:
an array of memory cells;
means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells;
means for non-temporarily storing the first addresses and the second addresses;
means for sensing the first addresses from the means for non-temporarily storing to obtain sensed first addresses;
means for detecting the second defective memory cells via the sensed first addresses; and
means for storing the second addresses in the means for temporarily storing and the means for non-temporarily storing.
16. The integrated circuit of claim 15, wherein the means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells includes:
means for temporarily storing the first addresses in first entries; and
means for temporarily storing the second addresses in second entries that are different than the first entries.
17. The integrated circuit of claim 16, wherein the means for temporarily storing first addresses of first defective memory cells and second addresses of second defective memory cells includes:
means for temporarily storing the sensed first addresses in the first entries.
18. The integrated circuit of claim 16, comprising:
means for graying out the first entries prior to storing the second addresses in the means for non-temporarily storing.
19. A method of repairing a memory, comprising:
sensing first addresses of first defective memory cells from non-volatile storage to obtain sensed first addresses;
detecting second defective memory cells via the sensed first addresses;
storing second addresses of the second defective memory cells in volatile storage; and
storing the second addresses in non-volatile storage via the volatile storage.
20. The method of claim 19, comprising:
storing the first addresses of the first defective memory cells in first entries of the volatile storage, wherein storing second addresses of the second defective memory cells in volatile storage comprises:
storing the second addresses of the second defective memory cells in second entries of the volatile storage, which are different than the first entries of the volatile storage.
21. The method of claim 20, comprising:
storing the sensed first addresses in the first entries of the volatile storage.
22. The method of claim 20, comprising:
graying out the first entries prior to storing the second addresses in the non-volatile storage via the volatile storage.
23. A method of repairing a memory, comprising:
detecting first defective memory cells;
storing first addresses of the first defective memory cells in volatile storage;
storing the first addresses of the first defective memory cells in non-volatile storage via the volatile storage;
sensing the first addresses from the non-volatile storage to obtain sensed first addresses;
detecting second defective memory cells via the sensed first addresses;
storing second addresses of the second defective memory cells in the volatile storage; and
storing second addresses of the second defective memory cells in the non-volatile storage via the volatile storage.
24. The method of claim 23, wherein:
storing first addresses of the first defective memory cells in volatile storage comprises storing the first addresses in first entries in the volatile storage;
storing second addresses of the second defective memory cells in the volatile storage comprises storing the second addresses in second entries in the volatile storage, which are different than the first entries in the volatile storage;
storing the first addresses of the first defective memory cells in non-volatile storage comprises storing the first addresses in third entries in the non-volatile storage; and
storing second addresses of the second defective memory cells in the non-volatile storage comprises storing the second addresses in fourth entries in the non-volatile storage, which are different than the third entries in the non-volatile storage.
25. The method of claim 24, wherein the first entries correspond to the third entries and the second entries correspond to the fourth entries and comprising:
graying out the first entries prior to storing the second addresses in the fourth entries of the non-volatile storage via the volatile storage.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor device comprising:
a silicon substrate constituting a base;
a semiconductor chip provided on said base and having a first main surface on which a plurality of electrode pads is provided, a surface protection film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protection film and said second main surface;
an insulating extension portion formed on said base so as to surround said side surfaces of said semiconductor chip;
a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the insulating extension portion;
a sealing resin formed on said wiring patterns, said insulating extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
2. The semiconductor device according to claim 1, wherein said electrode posts are formed from a conductive material.
3. The semiconductor device according to claim 1, wherein said external terminals are formed as solder balls.
4. The semiconductor device according to claim 1, wherein portions of the wiring patterns on a boundary and vicinity thereof between semiconductor chip and the extension portion are formed wider or more thickly than other portions of said wiring patterns.
5. The semiconductor device according to claim 1, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
6. The semiconductor device according to claim 5, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
7. The semiconductor device according to claim 1, wherein said semiconductor chip is in contact with said silicon substrate.
8. A semiconductor device comprising:
a silicon substrate constituting a base;
an extension portion having a concave portion which is formed from an insulating material and provided on said base;
a semiconductor chip having a first main surface on which a plurality of ejectrode pads are provided, a surface protection film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protection film and said second main surface, which is provided within the concave portion of said extension portion such that said side surfaces are surrounded by said extension portion;
a plurality of wiring patterns electrically connected to said electrode pads and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the extension portion;
a sealing resin formed on said wiring patterns, said extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
9. The semiconductor device according to claim 8, wherein said electrode posts are formed from a conductive material.
10. The semiconductor device according to claim 8, wherein portions of the wiring patterns on a boundary and vicinity thereof between semiconductor chip and the extension portion are formed wider or more thickly than other portions of said wiring patterns.
11. The semiconductor device according to claim 8, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
12. The semiconductor device according to claim 11, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a lower temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
13. The semiconductor device according to claim 8, wherein said extension portion is in contact with said silicon substrate.
14. A semiconductor device comprising:
a silicon substrate constituting a base;
an insulating extension portion provided on said base and having a concave portion having inclined inside walls;
a semiconductor chip comprising a first main surface on which a plurality of electrode pads is provided, a surface protecting film formed on said first main surface such that said electrode pads are exposed, a second main surface which opposes said first main surface, and a plurality of side surfaces between the surface of said surface protecting film and said second main surface, which is provided within the concave portion of said extension portion such that said side surfaces are surrounded by said extension portion;
an insulating film formed over the surface of said inside walls, the surface of said extension portion, and said surface protecting film such that a part of said electrode pads is exposed;
a plurality of wiring patterns formed on said insulating film, electrically connected to said electrode pads, and extended from said electrode pads to the surface of said extension portion;
a plurality of electrode posts formed on portions of said wiring patterns, the portions of said wiring patterns being arranged on the insulating extension portion;
a sealing resin formed on said wiring patterns, said insulating extension potion, and the side surfaces of the electrode posts; and
a plurality of external terminals provided on said electrode posts.
15. The semiconductor device according to claim 14, wherein said extension portion is formed from an insulating material having a greater molding shrinkage than the molding shrinkage of said sealing portion.
16. The semiconductor device according to claim 15, wherein said extension portion is formed from an insulating liquid resin having a linear expansion coefficient in a lower temperature range than glass transition point of less than 1.5\xd710\u22125\xb0 C. and a modulus of elasticity within a range of 7.8 to 22 GPa.
17. The semiconductor device according to claim 14, wherein said insulating extension is in contact with said silicon substrate.