1. A method comprising:
receiving an instruction to finalize data at a data storage device that includes a controller coupled to a semiconductor memory, wherein the data storage device further includes a status indicator to indicate a finalize status of the semiconductor memory; and
in response to receiving the instruction to finalize the data at the data storage device, setting the status indicator to a finalize value, wherein write to the semiconductor memory operations are prevented by the controller in response to the status indicator having the finalize value.
2. The method of claim 1, wherein erase from the semiconductor memory operations are prevented by the controller in response to the status indicator having the finalize value.
3. The method of claim 1, wherein setting the status indicator to the finalize value includes programming a persistent memory cell of the data storage device.
4. The method of claim 3, wherein the persistent memory cell is located at the controller.
5. The method of claim 3, wherein the persistent memory cell is located at the semiconductor memory.
6. The method of claim 1, wherein the controller and the semiconductor memory are integrated in a single semiconductor device.
7. The method of claim 1, wherein the controller is formed on a controller component and the semiconductor memory is formed on a storage component.
8. The method of claim 1, further comprising, in response to receiving the instruction to finalize the data at the semiconductor memory, setting a memory type indicator at the data storage device to a value that indicates a read-only memory type.
9. The method of claim 1, further comprising, in response to receiving the instruction to finalize the data at the semiconductor memory, setting a supported commands indicator at the data storage device to a value that indicates that data write operations to the semiconductor memory are not supported.
10. The method of claim 1, further comprising, in response to receiving the instruction to finalize the data at the semiconductor memory, setting a write protect indicator at the data storage device to a value that indicates that the semiconductor memory is write-protected.
11. The method of claim 1, further comprising, in response to receiving a query from a host device, reading a value of the status indicator and generating at least one of a value that indicates a memory type, a value that indicates whether data write operations are supported, or a value that indicates whether the semiconductor memory is write-protected, based on the value of the status indicator.
12. An apparatus comprising:
a memory controller; and
a storage interface circuit coupled to the memory controller,
wherein the memory controller is configured to finalize a semiconductor memory that is coupled to the memory controller via the storage interface circuit and set a status indicator to a finalize value in response to receiving an instruction from a host, and
wherein the memory controller is further configured to disable access of the host to write data to the semiconductor memory when the status indicator has the finalize value.
13. The apparatus of claim 12, wherein the status indicator is configured to persistently store the finalize value.
14. The apparatus of claim 13, wherein the memory controller includes a one-time programmable memory cell that stores at least a portion of the status indicator as a logical value.
15. The apparatus of claim 13, wherein the semiconductor memory includes a one-time programmable memory cell that stores at least a portion of the status indicator as a logical value.
16. The apparatus of claim 12, wherein the memory controller includes a status register, and wherein the status indicator includes at least one bit of the status register.
17. The apparatus of claim 12, wherein the semiconductor memory includes a flash memory cell and wherein at least a portion of the status indicator is stored at the flash memory cell.
18. The apparatus of claim 12, wherein the semiconductor memory is a flash memory and wherein the memory controller is further configured to, in response to receiving the instruction from the host to finalize the semiconductor memory, perform at least one cycle of erasing data from the flash memory and rewriting the data to the flash memory.
19. The apparatus of claim 12, wherein the memory controller is further configured to, in response to receiving the instruction from the host to finalize the semiconductor memory:
set a memory type indicator to a value that indicates a read-only memory type; and
send the value that indicates the read-only memory type to the host.
20. The apparatus of claim 12, wherein the memory controller, the storage interface circuit, and the semiconductor memory are integrated in a single semiconductor device.
21. The apparatus of claim 12, wherein the memory controller is formed on a controller component and the semiconductor memory is formed on a storage component.
22. An apparatus comprising:
a memory controller; and
a semiconductor memory coupled to the memory controller,
wherein the memory controller is configured to set a status indicator to a finalize value that indicates a finalize status of the semiconductor memory in response to receiving an instruction from a host to finalize the semiconductor memory, and
wherein the memory controller is further configured to block access of the host to write data to the semiconductor memory in response to the status indicator having the finalize value.
23. The apparatus of claim 22, wherein the status indicator is located at the memory controller.
24. The apparatus of claim 22, wherein the status indicator is located at the semiconductor memory.
25. The apparatus of claim 22, wherein the memory controller is configured to set at least a portion of the status indicator by programming a one-time programmable memory cell.
26. The apparatus of claim 22, wherein the memory controller is further configured to, in response to receiving the instruction to finalize the semiconductor memory, set at least one value of a register that is accessible to the host, the at least one value indicating that write operations to the semiconductor memory are not enabled.
27. The apparatus of claim 22, wherein the memory controller and the semiconductor memory are integrated in a single semiconductor device.
28. The apparatus of claim 22, wherein the memory controller is formed on a controller component and the semiconductor memory is formed on a storage component.
29. An apparatus comprising:
a memory controller;
a semiconductor memory responsive to the memory controller; and
an interface circuit coupled to the memory controller,
wherein the interface circuit enables communication between the memory controller and a host interface controller,
wherein the memory controller is configured to set a status indicator to a finalize value in response to receiving an instruction via the interface circuit, and
wherein the memory controller is further configured to disable access to write data to the semiconductor memory when the status indicator has the finalize value.
30. The apparatus of claim 29, further comprising a memory cell configured to persistently store at least a portion of the finalize value.
31. The apparatus of claim 29, wherein the semiconductor memory is a flash memory and wherein the memory controller is further configured to, in response to receiving the instruction to finalize the semiconductor memory, perform at least one cycle of erasing data from the flash memory and rewriting the data to the flash memory.
32. The apparatus of claim 29, wherein the memory controller and the semiconductor memory are integrated in a single semiconductor device.
33. The apparatus of claim 29, wherein the memory controller is configured to, in response to receiving a status read command via the interface circuit after setting the status indicator to the finalize value, provide a write protect indicator value via the interface circuit, wherein the write protect indicator value indicates that the semiconductor memory is write-protected.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A printer for printing of a page, the printer including
at least one inkjet printhead,
a printhead controller;
an interface for receiving data relating to the page to be printed, the data including a page description comprising a bi-level black layer and a contone color layer;
at least one raster image processor adapted to raster the received data and compress the rastered data;
the printhead controller including:
a decoding unit that extracts from the compressed rastered data first data relating to the bi-level black layer and second data relating to the contone color layer;
memory that temporarily stores the first and second data;
a ditherercompositor unit operable to:
produce a dithered bi-level color layer based on the second data,
produce a bi-level black layer based on the first data and
composite the bi-level black layer on the color layer after dithering thereof to produce a page image;
wherein the printhead controller controls the printhead to print the ditheredcomposited page image.
2. The printhead controller of claim 1 including a printhead interface that controls at least one printhead connected to the interface and that feeds the page image to the at least one printhead.
3. The printhead controller of claim 1 wherein the decoding unit includes a first decoded that extracts the first data and a second decoder that extracts the second data.
4. The printhead controller of claim 3 wherein the first and second decoders are arranged in parallel.
5. The printhead controller of claim 3 in which the first decoder is a lossless bi-level decompression device for decompressing the bi-level black layer.
6. The printhead controller of claim 3 in which the second decoder is a high-quality lossy decompression device for decompressing the contone color layer.
7. The printhead controller of claim 1 wherein the memory includes a first memory device that stores the first data and a second, physically distinct, memory device that stores the second data.
8. The printhead controller of claim 1, further including a third memory device that receives the page image.
9. The printhead controller of claim 8 in which each of the memory devices is a dedicated, on-chip FIFO.
10. The printhead controller of claim 1 that functions as a self-synchronizing pipeline.
11. A method of creating and printing a page image by a printer including at least one printhead, the method including:
receiving data to be printed including a page description comprising a bi-level black layer and a contone color layer, the data being received by the printer from a data source external to the printer;
rastering the data;
compressing the rastered data; and
storing the compressed rastered data in a memory;
in a printhead controller of the printer:
extracting first rastered data from said memory, said first data relating to the bi-level black layer from the compressed data;
extracting second rastered data from said memory, said second data relating to the contone color layer from the compressed data;
storing the extracted first and second rastered data in a local memory of the printhead controller;
retrieving the first and second data from the memory;
creating a dithered bi-level color layer from the second data;
creating bi-level black layer from the first data
compositing the bi-level black layer on the dithered bi-level color layer to create a ditheredcomposited page image, and
controlling the printhead to print the ditheredcomposited page image.
12. The method of claim 11 in which the first and second data are extracted substantially simultaneously.
13. The method of claim 11 that includes extracting the first data using a lossless bi-level decompression device.
14. The method of claim 11 that includes extracting the second data using a high quality lossy decompression device.
15. The method of claim 11, further including the step of temporarily storing the page image in a storage device prior to printing.
16. The method of claim 11 when performed in a printhead controller, including operating the printhead controller as a self-synchronizing pipeline.