1. A method for automatic color correction, comprising steps of:
constructing an operation window and a target window in said operation window on a plane coordinate system with two coordinate axes associated with a first chroma signal and a second chroma signal;
determining whether a first chroma value and a second chroma value of an image point are located between said operation window and said target window; and
adjusting said first and said second chroma values of said image point according to said target window only when said first and said second chroma values of said image point are located between said operation window and said target window.
2. The method for automatic color correction as recited in claim 1, wherein said first and said second chroma values of said image point are adjusted according to the location relationship between said image point and the boundary of said target window.
3. The method for automatic color correction as recited in claim 2, wherein said first and said second chroma values of said image point are adjusted according to the location relationship between said image point and a corresponding point on the boundary of said target window.
4. The method for automatic color correction as recited in claim 3, wherein said corresponding point on the boundary of said target window is determined according to an intersection of said target window and a line connected by said image point and a target point in said target window.
5. The method for automatic color correction as recited in claim 3, wherein said first and said second chroma values of said image point are adjusted according to the vector relationship between said image point and said corresponding point on the boundary of said target window.
6. The method for automatic color correction as recited in claim 5, wherein said image point, said corresponding point and said adjusted image point are denoted by A, B and A\u2032 respectively, and said adjusted image point A\u2032 is defined as:
A\u2032=A+Gain\xd7(B\u2212A)
where Gain is a gain coefficient.
7. The method for automatic color correction as recited in claim 6, wherein said gain coefficient varies within said operation window.
8. The method for automatic color correction as recited in claim 7, wherein said relationship between said gain coefficient and said operation window is defined by a look-up table (LUT).
9. The method for automatic color correction as recited in claim 7, wherein said relationship between said gain coefficient and said operation window is defined by a plurality of linear equations with different slopes on said plane coordinate system.
10. The method for automatic color correction as recited in claim 1, wherein said operation window is a rectangle or a rhombus.
11. The method for automatic color correction as recited in claim 1, wherein said target window is a rectangle or a rhombus.
12. The method for automatic color correction as recited in claim 1, wherein two points on said plane coordinate system respectively define said operation window and said target window.
13. The method for automatic color correction as recited in claim 1, wherein said target window is located at the center of said operation window.
14. The method for automatic color correction as recited in claim 1, wherein said target window is associated with an input luminance level of said image point.
15. A device for automatic color correction, comprising:
a comparative apparatus, receiving an operation window signal, a target window signal, a first chroma signal, and a second chroma signal so as to output a first comparative signal and a second comparative signal;
a logic gate, receiving said first comparative signal and said second comparative signal so as to output a control signal; and
a mapping value calculator, receiving said first chroma signal, said second chroma signal, and said control signal so as to generate a third chroma signal and a fourth chroma signal.
16. The device for automatic color correction as recited in claim 15, wherein said comparative apparatus further comprises:
a first comparator, receiving said first chroma signal, said second chroma signal, and said operation window signal so as to output said first comparative signal; and
a second comparator, receiving said first chroma signal, said second chroma signal, and said target window signal so as to output said second comparative signal.
17. The device for automatic color correction as recited in claim 15, wherein said logic gate is an AND gate.
18. The device for automatic color correction as recited in claim 15, wherein said logic gate is a NAND gate.
19. The device for automatic color correction as recited in claim 15, wherein said mapping value calculator further comprises:
a subtractor, receiving said first chroma signal, said second chroma signal, and said target window signal so as to output a vector signal;
a multiplier, receiving said vector signal and a gain signal so as to output a gain vector signal; and
an adder, receiving said first chroma signal, said second chroma signal, and said gain vector signal so as to output said third chroma signal and said fourth chroma signal.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A data output circuit for outputting a data a semiconductor memory device, comprising:
a clock generating circuit for receiving an input clock to output a high voltage clock and a low voltage clock;
a data transmitting unit for transmitting the data as high voltage data and low voltage data corresponding to the data in response to the high voltage clock and the low voltage clock, respectively; and
a data repeater for selectively outputting one of the high voltage data and the low voltage data in response to a voltage level check signal.
2. The data output circuit as recited in claim 1, wherein the data transmitting unit includes:
a level shifter for receiving the data to output the high voltage data in response to the high voltage clock; and
a data carrier for receiving the data to output the low voltage data in response to the low voltage clock.
3. The data output circuit as recited in claim 2, wherein the data repeater includes:
a high voltage data repeater for outputting the high voltage data as an output data when the voltage level check signal has a first logic level; and
a low voltage data repeater for outputting the low voltage data as the output data when the voltage level check signal has a second logic level.
4. The data output circuit as recited in claim 1, wherein the clock generating circuit includes:
a clock generator for generating a rising clock and a falling clock in response to the input clock; and
a clock repeater for transmitting the rising clock and the falling clock as the high voltage clock or the low voltage clock in response to the voltage level check signal.
5. The data output circuit as recited in claim 4, wherein the clock repeater includes:
a rising clock repeater receiving the rising clock to selectively output a high voltage rising clock and a low voltage rising clock in response to the voltage level check signal; and
falling clock repeater receiving the falling clock to selectively output a high voltage falling clock and a low voltage falling clock in response to the voltage level check signal.
6. The data output circuit as recited in claim 5, wherein the rising clock repeater includes:
a high voltage rising clock repeater for outputting the high voltage rising clock when the voltage level check signal has a first logic level; and
a low voltage rising clock repeater for outputting the low voltage rising clock when the voltage level check signal has a second logic level.
7. The data output circuit as recited in claim 5, wherein the falling clock repeater includes:
a high voltage falling clock repeater for outputting the high voltage falling clock when the voltage level check signal has a first logic level; and
a low voltage falling clock repeater for outputting the low voltage falling clock when the voltage level check signal has a second logic level.
8. The data output circuit as recited in claim 5, wherein the data includes a rising data for the rising clock and a falling data for the falling clock.
9. The data output circuit as recited in claim 8, wherein a data carrier includes:
a low voltage rising data transmitting unit for outputting the rising data as the low voltage data in response to the low voltage rising clock; and
a low voltage falling data transmitting unit for outputting the falling data as the low voltage data in response to the low voltage falling clock.
10. A method for outputting a data of a semiconductor memory device, comprising:
generating a rising clock and a falling clock in response to an input clock to;
receiving the rising clock and the falling clock to selectively output a high voltage clock and a low voltage clock in response to a voltage level check signal;
shifting the data to output a high voltage data and a low voltage data corresponding to the data in response to the high voltage clock and the low voltage clock, respectively; and
selectively outputting the high voltage data and the low voltage data in response to the voltage level check signal.
11. The data output method as recited in claim 10, wherein outputting the high voltage clock and the low voltage clock includes:
selectively outputting a high voltage rising clock and a low voltage rising clock corresponding to the rising clock in response to the voltage level check signal; and
selectively outputting a high voltage falling clock and a low voltage falling clock corresponding to the falling clock in response to the voltage level check signal.