1. A method of manufacturing a display substrate, the method comprising:
forming a TFT on a substrate, the substrate comprising an active area and an inactive area, the forming of the TFT being on the active area of the substrate;
forming an OLED electrically connected to the TFT and comprising a first electrode, an organic light-emitting layer and a second electrode;
concurrently or simultaneously forming a deposition assistant layer on a first region of the second electrode with a deposition assistant layer pattern on the inactive area of the substrate;
concurrently or simultaneously forming a conductive layer electrically connected to the second electrode, the forming of the conductive layer comprising depositing a conductive material on a second region of the second electrode, which excludes the first region, with a transmittance measurement pattern unit, the depositing of the transmittance measurement pattern unit comprising depositing the conductive material on the deposition assistant layer pattern; and
measuring transmittance of the transmittance measurement pattern unit to determine whether a defect is present.
2. The method of claim 1, wherein the forming of the deposition assistant layer and the deposition assistant layer pattern comprises using a mask having openings corresponding to regions in which the deposition assistant layer and the deposition assistant layer pattern are to be formed.
3. The method of claim 1, wherein the forming of the conductive layer and the transmittance measurement pattern unit comprises using a mask having openings corresponding to the active area and the transmittance measurement pattern unit.
4. The method of claim 1, wherein the measuring of the transmittance is performed directly after the forming of the conductive layer.
5. The method of claim 1, wherein the measuring of the transmittance is performed within a deposition chamber in which the conductive material is deposited.
6. The method of claim 1, wherein the measuring of the transmittance is performed while the substrate having the conductive material deposited thereon is being transferred.
7. The method of claim 1, wherein the measuring of the transmittance comprises:
irradiating light to the transmittance measurement pattern with a light emitter on a first side of the substrate; and
receiving light transmitted through the substrate and the transmittance measurement pattern with a light receiver on a second side of the substrate, facing oppositely away from the first side.
8. The method of claim 7, wherein light irradiated from the light emitter to the transmittance measurement pattern unit is perpendicular to the substrate.
9. The method of claim 1, wherein the second electrode is formed as a light-transmissive thin film.
10. The method of claim 1, wherein the second electrode comprises a metal selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, and an alloy thereof.
11. The method of claim 1, wherein the conductive material comprises Mg.
12. The method of claim 1, wherein a thickness of the conductive layer is equal to or greater than a thickness of the second electrode.
13. The method of claim 1, wherein the deposition assistant layer and the deposition assistant layer pattern comprises a light-transmitting material.
14. The method of claim 1, wherein the deposition assistant layer and the deposition assistant layer pattern comprise 8-quinolinolato lithium, N,N-diphenyl-N,N-bis(9-phenyl-9H-carbazol-3-yl)biphenyl-4,4\u2032-diamine, N(diphenyl-4-yl)9,9-dimethyl-N-(4(9-phenyl-9H-carbazol-3-yl)phenyl)-9H-fluorene-2-amine, or 2-(4-(9,10-di(naphthalene-2-yl)anthracene-2-yl)phenyl)-1-phenyl-1H-benzo-Dimidazole.
15. The method of claim 1, wherein adhesion between the conductive layer and the deposition assistant layer is weaker than adhesion between the conductive layer and the second electrode.
16. The method of claim 1, wherein the active area comprises a transmission region configured to transmit external light and a pixel region adjacent to the transmission region, wherein all or part of the transmission region and the pixel region are located in the first region of the second electrode, and wherein the first electrode is formed to overlap the pixel region.
17. The method of claim 16, wherein the first electrode is formed to overlap and hide the TFT.
18. The method of claim 17, wherein the transmission region is formed such that a ratio of an area of the transmission region to the sum of an area of the pixel region and the area of the transmission region is in a range of 5 to 90%.
19. The method of claim 1, further comprising outputting an alarm signal based on detection of the defect.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A solid-state device comprising the following circuits:
a plurality of adaptive amplifier modulator circuits; at least one radiofrequency digitizer circuit; a USB engine and microcode power selector interface; a PN code selective beamforming engine circuit; and a many input single output radio frequency (RF) combiner circuit,
wherein the PN code selective beamforming engine circuit comprises: a plurality of de-spreader circuits, a weight phasor angle circuit, a reference signal circuit, and a weight magnitude normalization circuit, the weight magnitude normalization circuit coupled to the adaptive amplifier modulator circuit, the reference signal circuit coupled to the weight magnitude normalization circuit and further coupled to the weight phasor angle circuit, and the plurality of de-spreader circuits, the weight phasor angle circuit coupled to the reference signal circuit and to the plurality of de-spreader circuits, and each de-spreader circuit further coupled to the at least one radiofrequency digitizer circuit by an amplitude input and a phase input and to the USB engine and microcode power selector interface.
2. The solid-state device of claim 1 wherein each adaptive amplifier modulator circuit comprises a low noise amplifier circuit, and a modulator circuit, the modulator circuit coupled to a radiofrequency output and the PN code selective beamforming engine circuit whereby the radiofrequency output is controlled by a plurality of weights, a radiofrequency input coupled to the low noise amplifier, and the at least one radiofrequency digitizer circuit coupled to the output of the low noise amplifier circuit.
3. The solid-state device of claim 1 wherein one of the plurality of adaptive amplifier modulator circuits comprises an integrated low noise amplifier modulator circuit; the integrated low noise amplifier modulator circuit coupled to a radiofrequency output and the PN code selective beamforming engine circuit whereby the radiofrequency output is controlled by a plurality of weights, a radiofrequency input coupled to the integrated low noise amplifier modulator circuit, and the at least one radiofrequency digitizer circuit coupled to the output of the integrated low noise amplifier modulator circuit.
4. The solid-state device of claim 1 wherein the adaptive amplifier modulator circuit further comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.
5. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises: a buffer, a sampler, a sampling oscillator, a switched capacitor analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor analog filter coupled between the digitizer and the sampler, the sampler further coupled between the sampling oscillator and the buffer and the buffer further coupled to the circuit input.
6. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises: a buffer, a sampler, an adjustable frequency sampling oscillator, a switched capacitor analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor analog filter coupled between the digitizer and the sampler, the sampler further coupled between the adjustable frequency sampling oscillator and the buffer and the buffer further coupled to the circuit input.
7. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit comprises: a buffer, a sampler, a sampling oscillator, a switched capacitor tunable analog filter, and a digitizer, the digitizer coupled to a PN code selective beamforming engine by a digital amplitude output and a digital phase output, the switched capacitor tunable analog filter coupled between the digitizer and the sampler, the sampler further coupled between the sampling oscillator and the buffer and the buffer further coupled to the circuit input.
8. The solid-state device of claim 5 wherein the sampling oscillator comprises a direct digital synthesizer driven by an on-chip oscillator and an external crystal to provide an adjustable frequency for under sampling a radiofrequency signal down and selecting the desired channel to pass through a channel filter.
9. The solid-state device of claim 1 wherein the at least one radiofrequency digitizer circuit further comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.
10. The device of claim 1 wherein each of the plurality of de-spreader circuits comprises a power conservation circuit coupled to the USB engine and microcode power selector interface.
11. The device of claim 1 wherein each of the plurality of de-spreader circuits comprises: a pair of inputs I and Q, a pair of digital multipliers, a pair of low pass filters, a code generator and acquisition and tracking circuit and a scale factor circuit, the scale factor circuit coupled to a circuit output and coupled to both inputs and both low pass filters, each digital multiplier coupled to a circuit input and to a low pass filter, the code generator and acquisition and tracking circuit coupled to an input and to each digital multiplier, and each low pass filter further coupled to a circuit output selected I and selected Q.
12. The de-spreader circuit of claim 11 wherein the code generator acquisition and tracking circuit is adapted to track a common pilot channel.
13. The de-spreader circuit of claim 11 wherein the code generator acquisition and tracking circuit is adapted to track a synchronization channel.
14. A solid-state device comprising the following circuits:
a plurality of adaptive amplifier modulator circuits; at least one radiofrequency digitizer circuit; a modem baseband processor and microcode power selector interface; a PN code selective beamforming engine circuit; and a many input single output radio frequency (RF) combiner circuit,
wherein the PN code selective beamforming engine circuit comprises: a plurality of de-spreader circuits, a weight phasor angle circuit, a reference signal circuit, and a weight magnitude normalization circuit, the weight magnitude normalization circuit coupled to the adaptive amplifier modulator circuit, the reference signal circuit coupled to the weight magnitude normalization circuit and further coupled to the weight phasor angle circuit, and the plurality of de-spreader circuits, the weight phasor angle circuit coupled to the reference signal circuit and to the plurality of de-spreader circuits, and each de-spreader circuit further coupled to the at least one radiofrequency digitizer circuit by an amplitude input and a phase input and to the USB engine and microcode power selector interface.
15. The device of claim 14 coupled to a multiple input multiple output modem configured in spatial multiplexing operational mode.
16. The device of claim 14 coupled to a multiple input multiple output modem configured in diversity combining operational mode.
17. The device of claim 14 coupled to a transmit path in a time-division duplexing system to produce a transmit phased array system.