What is claimed is:
1. A friction stir welding method comprising the steps of:
detecting, using a sensor, the position of the tip of a friction stir welding tool mounted on a main shaft;
setting as a reference position the position obtained by adding or subtracting the length of a small-diameter portion of said tool to said detected position; and
performing friction stir welding by inserting said tool into said reference position in a work object.
2. A friction stir welding method comprising the steps of:
detecting the torque, current value of a rotation axis of a friction stir welding tool during a friction stir welding process; and
controlling the depth of insertion of said friction stir welding tool into a work object based on the detected value.
3. A friction stir welding method comprising the steps of:
detecting the torque current value of a rotation axis when inserting a friction stir welding tool into a work object;
correcting the coordinate value of said work object based on said detected torque current value; and
controlling the relative amount of movement of said friction stir welding tool relative to said work object based on the corrected value.
4. A friction stir welding method comprising the steps of:
while inserting a friction stir welding tool into a work object, detecting a current flowing in said tool being transmitted when said tool contacts said work object;
correcting the coordinate value of said work object based on said detected current; and
controlling the relative amount of movement of said friction stir welding tool relative to said work object based on the corrected coordinate value.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A method of controlling a data strobe clock buffer in a semiconductor memory apparatus, comprising:
enabling a buffer enable signal;
generating an internal strobe clock signal by buffering an external data strobe clock signal pair;
disabling the buffer enable signal by discriminating toggle timing of the internal data strobe clock signal according to a burst length of data input to the semiconductor memory apparatus; and
stopping the buffering operation for the external data strobe clock signal pair.
2. The method of claim 1, wherein the disabling the buffer enable signal comprises:
generating a timing discrimination signal by discriminating the toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal; and
disabling the buffer enable signal in response to the timing discrimination signal.
3. The method of claim 2, wherein the timing discrimination signal includes a first timing discrimination signal and a second timing discrimination signal.
4. The method of claim 3, wherein the generating of the timing discrimination signal discriminates how many times the internal data strobe clock signal is toggled according to whether the burst length signal is enabled to enable the first timing discrimination signal.
5. The method of claim 4, wherein the generating of the timing discrimination signal further comprises generating the second timing discrimination signal having the same period as the internal data strobe clock signal and a pulse width narrower than the internal data strobe clock signal.
6. The method of claim 4, wherein the disabling the buffer enable signal in response to the timing discrimination signal disables the buffer enable signal if the second timing discrimination signal is toggled in a state where the first timing discrimination signal is enabled.
7. A method of controlling a semiconductor memory apparatus, comprising:
controlling a data strobe clock buffer of the semiconductor memory apparatus by:
starting a buffering operation for an external data strobe clock signal pair and enabling a buffer enable signal;
generating an internal strobe clock signal by buffering the external data strobe clock signal pair;
disabling the buffer enable signal by discriminating toggle timing of the internal data strobe clock signal according to a burst length of data input to the semiconductor memory apparatus; and
stopping the buffering operation for the external data strobe clock signal pair.
8. The method of claim 7, wherein the disabling the buffer enable signal is controlled by a timing discrimination signal generated by discriminating the toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal of the input data.
9. The method of claim 8, further comprising generating a two-period time delay signal based upon a level change after two time periods of the internal data strobe clock signal when the burst start signal is enabled.
10. The method of claim 9, further comprising delaying the two-period time delay signal by two time periods of the internal data strobe clock signal to generate a four- period time delay signal.
11. The method of claim 10, further comprising combining the two-period time delay signal and the four-period time delay signal based upon the burst length signal to disable the buffer enable signal.