1. A plasma display apparatus comprising:
a plasma display panel having a scan electrode and a sustain electrode; and
a driver for overlapping a peak voltage portion of at least one of sustain pulses supplied to the scan electrode with a peak voltage portion of at least one of sustain pulses supplied to the sustain electrode,
wherein the driver ensures that a last sustain pulse supplied to the scan electrode and a last sustain pulse supplied to the sustain electrode overlap with each other, and wherein a width of the last sustain pulse supplied to the scan electrode is different from a width of the last sustain pulse supplied to the sustain electrode.
2. The plasma display apparatus as claimed in claim 1, wherein the driver controls a number of sustain pulses that are overlapped with each other based on a reference average picture level (APL) of one frame.
3. The plasma display apparatus as claimed in claim 1, wherein the sustain pulses are overlapped with each other, when a number of cells in an on state is 20% or less of all of the cells in one frame.
4. The plasma display apparatus as claimed in claim 1, wherein the width of the last sustain pulse supplied to the scan electrode is greater than the width of the last sustain pulse supplied to the sustain electrode.
5. The plasma display apparatus as claimed in claim 1, wherein the width of the last sustain pulse supplied to the scan electrode is 1.2 to 1.8 times greater than the width of the last sustain pulse supplied to the sustain electrode.
6. The plasma display apparatus as claimed in claim 1, wherein a length of a period when the last sustain pulse supplied to the scan electrode and the last sustain pulse supplied to the sustain electrode overlap with each other is 0.2 to 0.3 times smaller than the width of the last sustain pulse supplied to the scan electrode.
7. A plasma display apparatus comprising:
a plasma display panel having a scan electrode and a sustain electrode; and
a driver for overlapping a peak voltage portion of a last sustain pulse applied to the sustain electrode with a peak voltage portion of a last sustain pulse applied to the scan electrode in a sustain period,
wherein a width of the last sustain pulse applied to the scan electrode is different from a width of the last sustain pulse applied to the sustain electrode.
8. The plasma display apparatus as claimed in claim 7, wherein the width of the last sustain pulse applied to the scan electrode is greater than the width of the last sustain pulse applied to the sustain electrode.
9. The plasma display apparatus as claimed in claim 7, wherein a lowest voltage of the last sustain pulse is applied to the scan electrode while the highest voltage of the last sustain pulse is applied to the sustain electrode.
10. A driving method of a plasma display apparatus, comprising:
supplying a scan pulse to a scan electrode in an address period; and
causing a peak voltage portion of at least one sustain pulse supplied to the scan electrode and a peak voltage portion of at least one sustain pulse supplied to a sustain electrode in a sustain period subsequent to the address period to overlap with each other,
wherein a last sustain pulse supplied to the scan electrode and a last sustain pulse supplied to the sustain electrode overlap with each other, and wherein a width of the last sustain pulse supplied to the scan electrode is substantially same as a width of the last sustain pulse supplied to the sustain electrode.
11. The driving method as claimed in claim 10, wherein a number of sustain pulses that are overlapped with each other is controlled based on a reference average picture level (APL) of one frame.
12. The driving method as claimed in claim 10, wherein the sustain pulses are overlapped with each other, when a number of cells in an on state is 20% or less of all of the cells in one frame.
13. The driving method as claimed in claim 10, wherein a width of the last sustain pulse supplied to the scan electrode is greater than a width of the last sustain pulse supplied to the sustain electrode.
14. The driving method as claimed in claim 10, wherein a width of the last sustain pulse supplied to the scan electrode is 1.2 to 1.8 times greater than a width of the last sustain pulse supplied to the sustain electrode.
15. The driving method as claimed in claim 10, wherein a length of a period when the last sustain pulse supplied to the scan electrode and the last sustain pulse supplied to the sustain electrode overlap with each other is 0.2 to 0.3 times smaller than a width of the last sustain pulse supplied to the scan electrode.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A semiconductor package comprising a lower package and an upper package stacked on the lower package, wherein the lower package includes:
a package substrate having upper and lower surfaces;
a semiconductor chip disposed on the upper surface of the package substrate;
a mold layer encapsulating the semiconductor chip; and
a residual stress layer disposed on the semiconductor chip, wherein the residual stress layer includes a plastically deformed surface,
wherein the residual stress layer has a residual stress to counterbalance warpage of the lower package.
2. The semiconductor package of claim 1, wherein the semiconductor chip includes an exposed surface not covered by the mold layer, and the residual stress layer is in contact with the exposed surface of the semiconductor chip.
3. The semiconductor package of claim 2, wherein the plastically deformed surface of the residual stress includes a plurality of first dents.
4. The semiconductor package of claim 3, wherein the plastically deformed surface of the residual stress layer has first roughness, and an upper surface of the mold layer has second roughness less than the first roughness.
5. The semiconductor package of claim 3, wherein the upper surface of the mold layer includes a plurality of second dents.
6. The semiconductor package of claim 5, wherein the plastically deformed surface includes first roughness caused by the plurality of first dents, and the upper surface of the mold layer includes second roughness caused by the plurality of second dents, and the second roughness is greater than the first roughness.
7. The semiconductor package of claim 2, wherein the upper surface of the mold layer is substantially coplanar with the exposed surface of the semiconductor chip, and the residual stress layer further extends onto the upper surface of the mold layer.
8. The semiconductor package of claim 1, wherein a lower surface of the package substrate includes a plurality of third dents.
9. The semiconductor package of claim 8, wherein the package substrate further comprises a pad, wherein a surface of the pad is a part of the lower surface of the package substrate.
10. The semiconductor package of claim 9, wherein roughness of the surface in the pad is less than roughness of the lower surface other than the surface of the pad.
11. A semiconductor package comprising:
a lower package including a lower semiconductor chip, a lower package substrate and a lower mold layer, wherein the lower semiconductor chip is mounted on the lower package substrate and the lower mold layer encapsulates the lower semiconductor chip;
an upper package stacked on the lower package, wherein the upper package includes an upper semiconductor chip, an upper package substrate and an upper mold layer and wherein the upper semiconductor chip is mounted on the upper package substrate and the upper mold layer encapsulates the upper semiconductor chip; and
a residual stress layer having a residual stress to counterbalance warpage of the lower package, wherein the residual stress layer is in contact with the lower package, and wherein the residual stress layer includes a plurality of first dents.
12. The semiconductor package of claim 11, wherein the residual stress layer is interposed between the lower package and the upper package.
13. (canceled)
14. The semiconductor package of claim 12, wherein the lower semiconductor chip includes an exposed surface, wherein the exposed surface of the lower semiconductor chip is not covered by the lower mold layer and faces the upper package, and wherein the residual layer covers the exposed surface of the lower semiconductor chip.
15. The semiconductor package of claim 14, wherein the lower mold layer includes an upper surface substantially coplanar with the exposed surface of the lower semiconductor chip, and wherein the residual stress layer further covers at least a portion of the upper surface of the lower mold layer.
16.-18. (canceled)
19. The semiconductor package of claim 14, wherein the upper surface of the lower mold layer includes a plurality of second dents, and wherein roughness of the upper surface of the lower mold layer is greater than roughness of a surface of the residual stress layer, wherein the surface of the residual stress layer faces the upper package.
20.-36. (canceled)
37. A semiconductor package comprising:
a lower package;
an upper package stacked on the lower package, wherein the lower package includes a surface having a plurality of dents.
38. The semiconductor package of claim 37, wherein the lower package includes a lower semiconductor chip, a lower package substrate and a lower mold layer,
wherein the lower semiconductor chip is mounted on an upper surface of the lower package substrate and the lower mold layer encapsulates the lower semiconductor chip,
wherein the plurality of dents is formed on an upper surface of the lower semiconductor chip and an upper surface of the lower mold layer, and
wherein the plurality of dents faces the upper package.
39. The semiconductor package of claim 37, wherein the lower package include a metal layer, a lower semiconductor chip, a lower package substrate and a lower mold layer,
wherein the lower semiconductor chip is mounted on an upper surface of the lower package substrate and the lower mold layer encapsulates the lower semiconductor chip,
wherein the metal layer is in contact with the lower semiconductor chip,
wherein the plurality of dents is formed on an upper surface of the metal layer, and wherein the plurality of dents faces the upper package.
40. The semiconductor package of claim 39, wherein the plurality of dents is further formed on an upper surface of the lower mold layer.
41. The semiconductor package of claim 39, wherein the plurality of dents is further formed on a lower surface of the lower semiconductor substrate.