1. An image processing apparatus for processing electronic image data obtained by an image pickup operation via an optical system, the image data having pixel data two-dimensionally-arranged in a row direction and a column direction, the image processing apparatus comprising:
a memory that stores the image data at least before image processing and further stores the image data after image procession;
a first data-order converting unit that sequentially reads the pixel data row by row in a row direction in units of a block of the two-dimensional arrangement of the image data via a bus from the memory and thereafter sequentially outputs the pixel data in the block obtained by reading column by column in the column direction to change an order of the image data;
an image processing unit that is connected to the first data-order converting unit for performing pipeline processing via an information sending channel different from the bus, inputting the image data outputted column by column in the column direction from the first data-order converting unit, performing image processing, and thereafter outputting the image data in the column direction; and
a second data-order converting unit connected to the image processing unit for performing pipeline processing and sequentially outputting column by column in the column direction, the image data in the block obtained by inputting the image processed image data outputted in the column direction from the image processing unit, to restore the original order of the image data,
wherein the image processing unit comprises a distortion correction processing unit that corrects distortion aberration caused by the optical system, and
wherein the distortion correction processing unit comprises:
an interpolating coordinate generating unit that generates interpolating coordinates;
an inner memory unit for storing a portion of the image data; and
an interpolation calculating unit for generating pixel data of interpolating coordinates from image data stored in the inner memory unit based on the interpolating coordinates generated by the interpolating coordinate generating unit.
2. The image processing apparatus according to claim 1, wherein the first data-order converting unit can change the size at least one of the image data in the row direction and the image data in the column direction read from the memory in units of a block.
3. The image processing apparatus according to claim 2, wherein the image data before the image procession is any of the following; the image pickup data that is obtained by photoelectrically converting, by image pickup means, a subject optical image formed by the optical system and outputted; non-compressed image data that is the image pickup data subjected, as occasion demands, to predetermined processing, excluding compressing processing; and compressed image data that is obtained by compressing processing after performing predetermined processing on the image pickup data, excluding the compressing processing, as occasion demands.
4. The image processing apparatus according to claim 1, wherein the image data before the image procession is any of the following; image pickup data that is obtained by photoelectrically converting, by image pickup means, a subject optical image formed by the optical system and outputted; non-compressed image data that is the image pickup data subjected, as occasion demands, to predetermined processing, excluding compressing processing; and compressed image data that is obtained by compressing processing after performing predetermined processing on the image pickup data, excluding the compressing processing, as occasion demands.
5. The image processing apparatus according to claim 1, wherein the interpolating-coordinate generating unit comprises:
an interpolating-position generating unit that generates coordinates of a pixel of an interpolating target in the image after correction of the distortion; and
a distortion-correcting-coordinate converting unit that obtains coordinates in the image before correction of the distortion, corresponding to the coordinates generated by the interpolating-position generating unit.
6. The image processing apparatus according to claim 5, wherein the interpolating-coordinate generating unit further comprises a selector that selects either of the coordinates generated by the interpolating-position generating unit or the coordinates obtained by the distortion-correcting-coordinate converting unit, and outputs the selected coordinates to the interpolation calculating unit.
7. The image processing apparatus according to claim 6, wherein the distortion-correcting-coordinate converting unit obtains coordinates in the image before correcting the distortion, corresponding to the coordinates generated by the interpolating-position generating unit, by using a predetermined correcting formula including a polynomial obtained by linearly combining the integer power of the distance from the center of distortion to the interpolating position.
8. The image processing apparatus according to claim 7, wherein the polynomial includes a term of a high degree of the distance, which is higher than the second degree.
9. The image processing apparatus according to claim 8, wherein the image processing unit further comprises another image processing unit other than the distortion correction processing unit, and
the distortion-correcting-coordinate converting unit outputs, to the other image processing unit, information on the distance from the center of distortion to the interpolating position.
10. The image processing apparatus according to claim 9, wherein the above-described another image processing unit comprises at least one of a shading correcting unit, a low-pass filter processing unit, and an edge-emphasis processing unit.
11. The image processing apparatus according to claim 7, wherein the image processing unit further comprises another image processing unit other than the distortion correction processing unit, and
the distortion-correcting-coordinate converting unit outputs, to the other image processing unit, information on the distance from the center of distortion to the interpolating position.
12. The image processing apparatus according to claim 11, wherein the above-described another image processing unit comprises at least one of a shading correcting unit, a low-pass filter processing unit, and an edge-emphasis processing unit.
13. The image processing apparatus according to claim 5, wherein the distortion-correcting-coordinate converting unit obtains coordinates in the image before correcting the distortion, corresponding to the coordinates generated by the interpolating-position generating unit, by using a predetermined correcting formula including a polynomial obtained by linearly combining the integer power of the distance from the center of distortion to the interpolating position.
14. The image processing apparatus according to claim 13, wherein the polynomial includes a term of a high degree of the distance, which is higher than the second degree.
15. The image processing apparatus according to claim 14, wherein the image processing unit further comprises another image processing unit other than the distortion correction processing unit, and
the distortion-correcting-coordinate converting unit outputs, to the other image processing unit, information on the distance from the center of distortion to the interpolating position.
16. The image processing apparatus according to claim 15, wherein the above-described another image processing unit comprises at least one of a shading correcting unit, a low-pass filter processing unit, and an edge-emphasis processing unit.
17. The image processing apparatus according to claim 13, wherein the image processing unit further comprises another image processing unit other than the distortion correction processing unit, and
the distortion-correcting-coordinate converting unit outputs, to the other image processing unit, information on the distance from the center of distortion to the interpolating position.
18. The image processing apparatus according to claim 17, wherein the above-described another image processing unit comprises at least one of a shading correcting unit, a low-pass filter processing unit, and an edge-emphasis processing unit.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A light emitting device driver circuit for driving a light emitting device circuit according to a rectified dimming signal, wherein a phase-cut dimming circuit converts an AC signal to an AC dimming signal, and a rectifier circuit converts the AC dimming signal to the rectified dimming signal, the light emitting device driver circuit comprising:
a power stage circuit, which is coupled to the rectifier circuit, for operating at least one power switch therein according to an operation signal, to convert the rectified dimming signal to an output signal, for driving the light emitting device circuit; and
a control circuit, for generating the operation signal according to a current sense signal related to a current flowing through the power switch, and a feedback signal related to the output signal, the control circuit including:
a pulse width modulation (PWM) circuit, for generating a PWM signal according to a level of the feedback signal;
a current limit (CL) circuit, for generating a CL signal according to the current sense signal and a predetermined current threshold, wherein the CL signal indicates whether the current sense signal reaches the predetermined current threshold; and
a determination circuit, which is coupled to the PWM circuit and the CL circuit, for generating the operation signal, and determining a duty of the operation signal according to one of the PWM signal and the CL signal;
wherein the power stage circuit operates the power switch according to the operation signal, to maintain an absolute level of an AC dimming current not lower than a holding current in an ON phase period;
wherein the operation signal is generated for a plurality of times in the ON phase period, wherein the duty of the operation signal in a portion of the times is decided by the PWM signal, and the duty of the operation signal in another portion of the times is determined by the CL signal;
wherein the AC dimming signal includes the AC dimming current flowing through the phase-cut dimming circuit, and the phase-cut dimming circuit blocks an OFF phase period of the AC signal and retains the ON phase period of the AC signal, to generate the AC dimming signal.
2. The light emitting device driver circuit of claim 1, wherein the determination circuit includes:
a logic gate circuit, which is coupled to the PWM circuit and the CL circuit, for generating a reset signal according to the PWM signal and the CL signal; and
a flip-flop circuit, which is coupled to the logic gate circuit, for generating the control signal according to the reset signal and a set signal, wherein the set signal is related to a clock signal or the feedback signal;
wherein a start time point of the duty of the operation signal is determined by the set signal, and an end time point of the duty of the operation signal is determined by the reset signal.
3. The light emitting device driver circuit of claim 1, wherein the PWM circuit includes:
an error amplifier circuit, for generating an error amplified signal according to the feedback signal and a reference signal; and
a comparison circuit, which is coupled to the error amplifier circuit, for generating the PWM signal according to the error amplified signal and a ramp signal.
4. The light emitting device driver circuit of claim 1, which is not connected to a bleeder circuit in parallel, wherein the bleeder circuit is for consuming a bleeding current which does not flow through the light emitting device circuit to maintain the absolute level of the AC dimming current not lower than the holding current in the ON phase period.
5. The light emitting device driver circuit of claim 1, wherein the current limit (CL) signal is for maintaining the absolute level of the AC dimming current not lower than the holding current in the ON phase period.
6. The light emitting device driver circuit of claim 1, wherein the power stage circuit includes:
a first winding, which is coupled to the rectifier circuit and the power switch, for receiving the rectified dimming signal and determining a switch current flowing through the power switch according to an operation of the power switch;
a second winding, which is coupled to the first winding, for generating the output signal according to the rectified dimming signal and the switch current, the output signal being provided to the light emitting device circuit; and
a third winding, which is coupled to the second winding, for generating a sense signal according to the output signal.
7. The light emitting device driver circuit of claim 6, wherein the first winding and the second winding are connected in series, to form a tapped inductor.
8. The light emitting device driver circuit of claim 6, wherein the power stage circuit further includes a voltage divider circuit, which is coupled to the third winding, for obtaining a divided voltage of the sense signal to generate the feedback signal.
9. A control method of a light emitting device driver circuit, wherein the light emitting device driver circuit is for driving a light emitting device circuit according to a rectified dimming signal, wherein a phase-cut dimming circuit converts an AC signal to an AC dimming signal, and a rectifier circuit converts the AC dimming signal to the rectified dimming signal, the control method comprising:
operating at least one power switch according to an operation signal, to convert the rectified dimming signal to an output signal for driving the light emitting device circuit, and to maintain an absolute level of an AC dimming current not lower than a holding current in an ON phase period;
generating a PWM signal according to a level of a feedback signal related to the output signal;
generating a current limit (CL) signal according to a current sense signal and a predetermined current threshold, the current sense signal being related to a current flowing thorough the power switch, wherein the CL signal indicates whether the current sense signal reaches the predetermined current threshold; and
generating the operation signal according to the PWM signal and the CL signal, and determining a duty of the operation signal according to one of the PWM signal and the CL signal;
wherein the operation signal is generated for a plurality of times in the ON phase period, wherein the duty of the operation signal in a portion of the times is decided by the PWM signal, and the duty of the operation signal in another portion of the times is determined by the CL signal;
wherein the AC dimming signal includes the AC dimming current flowing through the phase-cut dimming circuit, and the phase-cut dimming circuit blocks an OFF phase period of the AC signal and retains the ON phase period of the AC signal, to generate the AC dimming signal.
10. The control method of claim 9, wherein the step of generating the operation signal according to the PWM signal and the CL signal includes:
generating a reset signal by performing a logic operation of the PWM signal and the CL signal; and
inputting the reset signal and a set signal to a flip-flop circuit, to generate the control signal, wherein the set signal is related to a clock signal or the feedback signal;
wherein a start time point of the duty of the operation signal is determined by the set signal, and an end time point of the duty of the operation signal is determined by the reset signal.
11. The control method of claim 9, wherein the step of generating a PWM signal according to a level of a feedback signal related to the output signal includes:
comparing the feedback signal and a reference signal, or a signal related to the feedback signal and a reference signal, to generate an error amplified signal; and
comparing the error amplified signal and a ramp signal to generate the PWM signal.
12. The control method of claim 9, wherein the current limit (CL) signal is for maintaining the absolute level of the AC dimming current not lower than the holding current in the ON phase period.
13. A control circuit of a light emitting device driver circuit, wherein the light emitting device driver circuit is for driving a light emitting device circuit according to a rectified dimming signal, wherein a phase-cut dimming circuit converts an AC signal to an AC dimming signal, and a rectifier circuit converts the AC dimming signal to the rectified dimming signal, wherein the light emitting device driver circuit includes a power stage circuit and the control circuit, wherein the power stage circuit is coupled to the rectifier circuit, for operating at least one power switch therein according to an operation signal, to convert the rectified dimming signal to an output signal, for driving the light emitting device circuit, the control circuit generating the operation signal according to a current sense signal and a feedback signal, wherein the current sense signal is related to a current flowing through the power switch, and the feedback signal is related to the output signal, the control circuit comprising:
a pulse width modulation (PWM) circuit, for generating a PWM signal according to a level of the feedback signal;
a current limit (CL) circuit, for generating a CL signal according to the current sense signal and a predetermined current threshold, wherein the CL signal indicates whether the current sense signal reaches the predetermined current threshold; and
a determination circuit, which is coupled to the PWM circuit and the CL circuit, for generating the operation signal, and determining a duty of the operation signal according to one of the PWM signal and the CL signal;
wherein the power stage circuit operates the power switch according to the operation signal, to maintain an absolute level of an AC dimming current not lower than a holding current in an ON phase period;
wherein the operation signal is generated for a plurality of times in the ON phase period, wherein the duty of the operation signal in a portion of the times is decided by the PWM signal, and the duty of the operation signal in another portion of the times is determined by the CL signal;
wherein the AC dimming signal includes the AC dimming current flowing through the phase-cut dimming circuit, and the phase-cut dimming circuit blocks an OFF phase period of the AC signal and retains the ON phase period of the AC signal, to generate the AC dimming signal.
14. The control circuit of claim 13, wherein the determination circuit includes:
a logic gate circuit, which is coupled to the PWM circuit and the CL circuit, for generating a reset signal according to the PWM signal and the CL signal; and
a flip-flop circuit, which is coupled to the logic gate circuit, for generating the control signal according to the reset signal and a set signal, wherein the set signal is related to a clock signal or the feedback signal;
wherein a start time point of the duty of the operation signal is determined by the set signal, and an end time point of the duty of the operation signal is determined by the reset signal.
15. The control circuit of claim 13, wherein the PWM circuit includes:
an error amplifier circuit, for generating an error amplified signal according to the feedback signal and a reference signal; and
a comparison circuit, which is coupled to the error amplifier circuit, for generating the PWM signal according to the error amplified signal and a ramp signal.
16. The control circuit of claim 13, wherein the light emitting device driver circuit is not connected to a bleeder circuit in parallel, wherein the bleeder circuit is for consuming a bleeding current which does not flow through the light emitting device circuit to maintain the absolute level of the AC dimming current not lower than the holding current in the ON phase period.
17. The control circuit of claim 13, wherein the current limit (CL) signal is for maintaining the absolute level of the AC dimming current not lower than the holding current in the ON phase period.