1. A semiconductor system comprising:
a first semiconductor chip configured to perform a parallel test according to a first single chip parallel test signal and a multi-chip parallel test signal, and output first data indicating pass or fail;
a second semiconductor chip configured to perform a parallel test according to a second single chip parallel test signal and the multi-chip parallel test signal, and output second data indicating pass or fail information; and
a data receiver configured to receive the first and second data as input data.
2. The semiconductor system of claim 1, wherein the first data is output in a high impedance state when the first semiconductor chip is normal.
3. The semiconductor system of claim 1, wherein the second data is output in a high impedance state when the second semiconductor chip is normal.
4. The semiconductor system of claim 1, wherein the data receiver comprises:
a switch unit configured to supply a first voltage to a first node, and supply a second voltage to the first node when a multi-chip parallel test is performed; and
a resistor coupled between the first node and a second node, wherein the input data is received.
5. The semiconductor system of claim 1, wherein the first semiconductor chip comprises:
a data compression unit configured to compress a plurality of data outputted from the memory unit and generate compressed data when a single chip parallel test or multi-chip parallel test is performed; and
a data output unit configured to generate a first pull-up signal and a first pull-down signal from the compressed data to drive the first data, in response to at least one of the first single chip parallel test signal and the multi-chip parallel test signal.
6. The semiconductor system of claim 5, wherein the first pull-up signal is disabled to a high level by the multi-chip parallel test signal when a multi-chip parallel test is performed.
7. The semiconductor system of claim 5, wherein the data output unit comprises:
a pull-up signal generation section configured to generate the first pull-up signal in response to the compressed data, first single chip parallel test signal, and the multi-chip parallel test signal;
a pull-down signal generation section configured to generate the first pull-down signal in response to the compressed data and the first single chip parallel test signal; and
a driving section configured to drive the first data in response to the first pull-up signal and the first pull-down signal.
8. The semiconductor system of claim 1, wherein the second semiconductor chip comprises:
a data compression unit configured to compress a plurality of data outputted from the memory unit and generate compressed data, when a single chip parallel test or multi-chip parallel test is performed; and
a data output unit configured to generate a second pull-up signal and a second pull-down signal from the compressed data to drive the second data, in response to at least one of the second single chip parallel test signal and the multi-chip parallel test signal.
9. The semiconductor system of claim 8, wherein the second pull-up signal is disabled to a high level by the multi-chip parallel test signal when a multi-chip parallel test is performed.
10. The semiconductor system of claim 8, wherein the data output unit comprises:
a pull-up signal generation section configured to generate the second pull-up signal in response to the compressed data, the second single chip parallel test signal, and the multi-chip parallel test signal;
a pull-down signal generation section configured to generate the second pull-down signal in response to the compressed data and the second single chip parallel test signal; and
a driving section configured to drive the second data in response to the second pull-up signal and the second pull-down signal.
11. A data output circuit comprising:
a driving unit configured to drive data in response to a pull-up signal and a pull-down signal;
a pull-up signal generation unit configured to generate the pull-up signal from compressed data generated by compressing a plurality of output data, a single chip parallel test signal, and a multi-chip parallel test signal,
wherein the pull-up signal is deasserted when a multi-chip parallel test is performed in response to a multi-chip parallel test signal; and
a pull-down signal generation unit configured to generate the pull-down signal from the compressed data and a single chip parallel test signal, wherein the pull-down signal is deasserted when the single-chip parallel test signal is deasserted.
12. The data output circuit of claim 11, wherein the pull-up signal is asserted when the compressed data indicates success, the single chip parallel test signal is asserted, and the multi-chip parallel test signal is asserted.
13. The data output circuit of claim 11, wherein the pull-down signal is asserted when the compressed data indicates failure and the single chip parallel test signal is asserted.
14. A method for generating an output signal at a specific chip, comprising:
generating a compressed data signal that indicates whether there was a failure in a test of at least a portion of the specific chip;
generating a pull-up signal from the compressed data signal, a multi-chip test enable signal that is used to indicate to multiple chips to simultaneously run the test, and a single test enable signal that indicates to the specific chip to run the test;
generating a pull-down signal from the compressed data signal and the single test enable signal; and
generating an output signal from an output circuit controlled by at least the pull-up signal and the pull-down signal.
15. The method according to claim 14, comprising asserting the pull-up signal when the multi-chip test enable signal is asserted, the compressed data signal indicates that there is no failure, and the single chip test enable signal is asserted.
16. The method according to claim 14, comprising asserting the pull-down signal when the single chip test enable signal is asserted and the compressed data signal indicates that there is no failure.
17. The method according to claim 14, wherein the pull-up signal and the pull-down signal controls the output circuit.
18. The method according to claim 17, wherein the output circuit is in a high-impedance output state when the pull-up signal and the pull-down signal are both deasserted.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A computer readable medium having computer readable program code used to direct a computer to perform advanced leveraging for translation, said program code performing steps of:
creating an index structure on a computer by parsing a target string;
matching said index structure to index structures previously stored on the computer; and
obtaining a translation of the target string using said index structure, wherein said index structure comprises phrasal and sub-phrasal markers, each marker having a constituent, a constituent name, and a number.
2. The program code according to claim 1, wherein the structure is a tree structure.
3. The program code according to claim 1, wherein the number is an index_entry_range.
4. The program code according to claim 1, wherein each marker is obtained by parsing a target string.
5. The program code according to claim 5, wherein the parsing identifies the constituent, the constituent name, and the numbers in the target string.
6. A method for perform advanced leveraging for translation, comprising steps of:
creating an index structure on a computer by parsing a target string;
matching said index structure to index structures previously stored on the computer; and
obtaining a translation of the target string using said index structure, wherein said index structure comprises phrasal and sub-phrasal markers, each marker having a constituent, a constituent name, and a number.
7. The method according to claim 6, wherein the structure is a tree structure.
8. The method according to claim 6, wherein the number is an index_entry_range.
9. The method according to claim 6, wherein each marker is obtained by parsing a target string.
10. The method according to claim 9, wherein the parsing identifies the constituent, the constituent name, and the numbers in the target string.