1. A domain authentication method for exchanging content between devices, comprising the steps of:
setting domain identification information into a predetermined device connected on one of a wired network and a wireless network, and
generating a domain secret key using the set domain identification information.
2. A domain authentication method for exchanging content between devices, comprising the steps of:
setting domain identification information into a predetermined device connected on one of a wired network and a wireless network, and
generating a domain secret key using the set domain identification information and predetermined device identification information.
3. A domain authentication method for exchanging content between devices, comprising:
a first step of setting domain identification information into a predetermined device connected on one of a wired network and a wireless network;
a second step of generating a domain secret key using the set domain identification information and predetermined device identification information;
a third step of generating a predetermined first code value and transmitting a first packet encrypted with the first code value using the domain secret key generated in the second step;
a fourth step of receiving a second packet that is encrypted with the first code value, which has been decrypted from the first encrypted packet using the domain secret key generated in the second step, and a second code value generated by another device; and
a fifth step of decrypting the second packet received in the fourth step by using the domain secret key generated in the second step and determining whether a specific bit frame of the decrypted second packet is equal to the predetermined first code value generated in the third step.
4. The method as claimed in claim 3, wherein the domain secret key is set as a resultant value of a cryptographic one-way function whose input variables are the domain identification information and the device identification information.
5. The method as claimed in claim 3, wherein the domain secret key is set as a resultant value of a hash function whose input variables are the domain identification information and the device identification information.
6. The method as claimed in claim 3, wherein the first and second code values are predetermined bits of random numbers generated by the devices themselves, respectively.
7. The method as claimed in claim 3, wherein the fifth step further comprises the step of generating a session key to be used for content encryption when the specific bit frame of the second decrypted packet is equal to the predetermined first code value generated in the third step, or terminating a domain authentication process when the specific bit frame is not equal to the first code value.
8. The method as claimed in claim 3, wherein the fifth step further comprises the step of transmitting another specific bit frame, which is based on the second decrypted packet, when the specific bit frame of the decrypted packet is equal to the predetermined first code value generated in the third step.
9. A domain authentication method for exchanging content between devices, comprising;
a first step of performing mutual authentication for the devices using device identification information;
a second step of setting domain identification information into a predetermined device connected on one of a wired network and a wireless network;
a third step of generating a domain secret key using the set domain identification information and the predetermined device identification information;
a fourth step of generating a predetermined first code value and transmitting a first packet encrypted with the first code value using the domain secret key generated in the third step;
a fifth step of receiving a second packet that is encrypted with the first code value, which has been decrypted from the first encrypted packet using the domain secret key generated in the third step, and a second code value generated by another device; and
a sixth step of decrypting the second packet received in the fifth step by using the domain secret key generated in the third step and determining whether a specific bit frame of the decrypted second packet is equal to the predetermined first code value generated in the fourth step.
10. The method as claimed in claim 9, wherein the domain secret key is set as a resultant value of a cryptographic one-way function whose input variables are the domain identification information and the device identification information.
11. The method as claimed in claim 9, wherein the domain secret key is set as a resultant value of a hash function whose input variables are the domain identification information and the device identification information.
12. The method as claimed in claim 9, wherein the first and second code values are predetermined bits of random numbers generated by the devices themselves, respectively.
13. The method as claimed in claim 9, wherein the sixth step further comprises the step of generating a session key to be used for content encryption when the specific bit frame of the second decrypted packet is equal to the predetermined first code value generated in the fourth step, or terminating a domain authentication process when the specific bit frame is not equal to the first code value.
14. The method as claimed in claim 9, wherein the sixth step further comprises the step of transmitting another specific bit frame, which is based on the second decrypted packet, when the specific bit frame of the decrypted packet is equal to the predetermined first code value generated in the fourth step.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A process for preparing a stressed semiconductor wafer, said process comprising:
providing a semiconductor wafer of a first material having a first crystalline lattice constant;
pseudomorphically forming a stressed crystalline layer of a second material having a different crystalline lattice constant from the first material on a surface of the semiconductor wafer;
etching a first via through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer;
filling the first via in the semiconductor wafer with a first filler material to impede dissipation of stress in the semiconductor wafer; and
removing the stressed crystalline layer after filling the first via in the semiconductor wafer.
2. A process for preparing a device including a stressed semiconductor wafer, said process comprising:
providing a semiconductor wafer of a first material having a first crystalline lattice constant;
pseudomorphically forming a stressed crystalline layer of a second material having a different lattice constant from the first material on a surface of the semiconductor wafer;
etching a first via through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer;
filling the first via in the stressed semiconductor wafer with a first filler material to impede dissipation of stress in the stressed region of the semiconductor wafer;
removing the stressed crystalline layer after filling the first via in the semiconductor wafer; and
forming a transistor on the stressed semiconductor wafer within the stressed region thereof.
3. The process of claim 2, further comprising forming at least one level of interconnect routing over the transistor on the semiconductor wafer.
4. (canceled)
5. (canceled)
6. The process of claim 2, wherein the second material has a greater crystalline lattice constant than the first material and wherein pseudomorphically forming the stressed crystalline layer of the second material on the surface of the semiconductor wafer comprises pseudomorphically forming the stressed crystalline layer under compressive stress on the surface of the semiconductor wafer.
7. The process of claim 6, wherein providing the semiconductor wafer comprises providing a silicon-containing wafer and wherein pseudomorphically forming the stressed crystalline layer comprises pseudomorphically forming a silicon germanium layer on the surface of the silicon-containing wafer.
8. The process of claim 7, wherein providing the silicon-containing wafer comprises providing the silicon-containing wafer comprising silicon in an amount of from about 95 to about 100 mol % based upon the total amount of atoms in the silicon-containing wafer and wherein pseudomorphically forming the silicon germanium layer is further defined as pseudomorphically forming the silicon germanium layer having a germanium content of from about 20 to about 40 mol % based upon the total amount of atoms in the silicon germanium layer.
9. The process of claim 7, wherein providing the silicon-containing wafer comprises providing the silicon-containing wafer having a thickness of from about 50 to about 1500 nm and wherein pseudomorphically forming the silicon germanium layer comprises pseudomorphically forming the silicon germanium layer having a thickness of from about 50 to about 1500 nm.
10. The process of claim 2, wherein the second material has a lesser crystalline lattice constant than the first material and wherein pseudomorphically forming the stressed crystalline layer of the second material on the surface of the semiconductor wafer comprises pseudomorphically forming the stressed crystalline layer under tensile stress on the surface of the semiconductor wafer.
11. The process of claim 10, wherein providing the semiconductor wafer comprises providing a silicon-containing wafer and wherein pseudomorphically forming the stressed crystalline layer comprises pseudomorphically forming a silicon carbide layer on the surface of the silicon-containing wafer.
12. The process of claim 11, wherein providing the silicon-containing wafer comprises providing the silicon-containing wafer comprising silicon in an amount of from about 95 to about 100 mol % based upon the total amount of atoms in the silicon-containing wafer and wherein pseudomorphically forming the silicon carbide layer is further defined as pseudomorphically forming the silicon carbide layer having a carbon content of from about 20 to about 40 mol % based upon the total amount of atoms in the silicon carbide layer.
13. The process of claim 11, wherein providing the silicon-containing wafer comprises providing the silicon-containing wafer having a thickness of from about 50 to about 1500 nm and wherein pseudomorphically forming the silicon carbide layer comprises pseudomorphically forming the silicon carbide layer having a thickness of from about 50 to about 1500 nm.
14. The process of claim 2, wherein providing the semiconductor wafer comprises providing the semiconductor wafer formed from the first material chosen from silicon germanium, germanium, gallium arsenide, or indium phosphide.
15. The process of claim 2, wherein etching the first via through the stressed crystalline layer and at least partially into the semiconductor wafer comprises etching the first via into the semiconductor wafer to a depth of from about 10 to about 100 nm from the surface of the semiconductor wafer, provided that the first via is only partially etched into the semiconductor wafer.
16. The process of claim 2, wherein filling the first via in the semiconductor wafer is further defined as epitaxially forming crystalline filler material in the first via.
17. The process of claim 2, wherein filling the first via in the semiconductor wafer is further defined as filling the first via in the semiconductor wafer with an electrically-conductive material.
18. The process of claim 2, further comprising etching a second via through the stressed crystalline layer and at least partially into the semiconductor wafer, with the stressed region of the semiconductor wafer disposed between the first via and the second via, to release stress in the stressed crystalline layer adjacent the second via.
19. The process of claim 18, further comprising filling the second via in the semiconductor wafer with a second filler material to further impede dissipation of stress in the stressed region of the semiconductor wafer.
20. A process for preparing a stressed semiconductor wafer, said process comprising:
providing a semiconductor wafer of a first material having a first crystalline lattice constant;
pseudomorphically forming a stressed crystalline layer of a second material having a different lattice constant from the first material on a surface of the semiconductor wafer;
etching a first via and a second via through the stressed crystalline layer and at least partially into the semiconductor wafer to release stress in the stressed crystalline layer adjacent the first via, thereby transferring stress to the semiconductor wafer and forming a stressed region in the semiconductor wafer with the stressed region of the semiconductor wafer disposed between the first via and the second via; and
filling the first via and the second via in the semiconductor wafer with a first filler material and a second filler material to impede dissipation of stress in the semiconductor wafer;
removing the stressed crystalline layer from the semiconductor wafer after filling the first via and the second via in the semiconductor wafer.