1. A traveling wave amplifier (TWA), comprising:
a plurality of non-inverting amplifiers, each of non-inverting amplifiers being put in parallel between an input and an output of the TWA and providing a signal in the output with a first delay with respect to the input; and
an inverting amplifier put between the input and the output of the TWA to provide another signal in the output with a second delay longer than the first delay.
2. The TWA of claim 1,
wherein the non-inverting amplifiers and the inverting amplifier have a configuration same with others and the inverting amplifier provides a transmission line connected to an output of the inventing amplifier,
wherein the transmission line causes a delay between the second delay and the first delay.
3. The TWA of claim 1,
wherein the non-inverting amplifiers and the inverting amplifier have a configuration same with others; and the inverting amplifier accompanies with another amplifier connected in series to the inverting amplifier,
wherein the other amplifier causes a delay between the second delay and the first delay.
4. The TWA of claim 1,
wherein the non-inverting amplifiers and the inverting amplifier are a differential amplifier.
5. The TWA of claim 4,
wherein the differential amplifier includes a pair of transistors whose collector-emitter bias is set in a quasi-saturated region.
6. The TWA of claim 5,
wherein the transistors in the differential amplifier are made of InP based semiconductor material.
7. A driver for driving a semiconductor modulator, comprising:
an input to receive an input signal;
an output to output an output signal to the semiconductor modulator;
an N count of non-inverting amplifiers, where N is an integer at least 1, wherein each of the non-inverting amplifiers has an arrangement substantially same to each other and configured to be connected in parallel between the input and the output, to receive the input signal with an input delay of td\xd7n (1<=n<=N, td: unit delay), and to provide an amplified signal to the output with an output delay of td\xd7(N\u2212n); and
a pre-emphasis unit connected in parallel to the non-inverting amplifiers between the input and the output of the driver, the pre-emphasis unit receiving the input signal with substantially no delay and providing a phase inverted signal to the output with an output delay of td\u2032+td\xd7(N\u22121),
wherein td\u2032 is longer than td.
8. The driver of claim 7,
wherein nth non-inverting amplifier includes an input terminal coupled to an input terminal of (n\u22121)th non-inverting amplifier with a transmission line of a first type, and an output terminal coupled to an output terminal of (n+1)th non-inverting amplifier with a transmission line of a first type,
wherein the pre-emphasis unit includes an inverting amplifier having an arrangement substantially same with an arrangement of the non-inverting amplifier, the inverting amplifier including an input terminal connected to the input of the driver and an output terminal connected with the output terminal of the first non-inverting amplifier with a transmission line of a second type,
wherein the transmission line of the first type causes the unit delay td, and the transmission line of the second type causes another unit delay td\u2032.
9. The driver of claim 7,
wherein the pre-emphasis unit includes an inverting amplifier and a non-inverting amplifier connected in series to and downstream of the inverting amplifier,
wherein the inverting amplifier receives the input signal with substantially no delay, and the non-inverting amplifier of the pre-emphasis unit provides the phase inverted signal to the output,
wherein the inverting amplifier causes a difference between the other unit delay td\u2032 and the unit delay td.
10. The driver of claim 7,
wherein the non-inverting amplifiers, the pre-emphasis unit have a differential amplifier, and the input signal have a differential arrangement.
11. A traveling wave amplifier (TWA) having an input terminal for receiving an input signal and an output terminal for outputting an amplified signal, comprising:
an input delay line including a plurality of delay elements;
an output delay line including a plurality of delay elements;
a plurality of first amplifiers having an input node and an output node, the input node being connected to a node between two delay elements of the input delay line, the output node being connected to a node between two delay elements of the output delay line, the first amplifier providing a portion of the amplified signal with a first delay from the input terminal and the output terminal; and
a second amplifier having an input node and an output node, the input node of the second amplifier receiving the input signal, the output node of the second amplifier connected to one of delay elements of the output delay line unbound with the first amplifiers, the second amplifier providing another portion of the amplified signal with a second delay longer than the first delay and by reversing a phase thereof.
12. The TWA of claim 11,
wherein the delay elements of the input delay line and the delay elements of the output delay line except for the one of delay elements of the output delay line cause a first unit delay, and
wherein one of delay elements of the output delay line causes a second unit delay longer than the first unit delay.
13. The TWA of claim 11,
wherein the delay elements of the input delay line and the delay elements of the output delay line cause a first unit delay, and
wherein the second amplifier includes an inverting amplifier and a non-inverting amplifier connected in series to the inverting amplifier, the inverting amplifier having the input node of the second amplifier, the non-inverting amplifier having the output node of the second amplifier and an arrangement same as an arrangement of the first amplifiers,
wherein the inverting amplifier in the second amplifier causes a second unit delay.
14. The TWA of claim 11,
wherein the input delay line, the output delay line, the first amplifiers, and the second amplifier have a differential arrangement.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
That which is claimed is:
1. A circuit (SYNC_ASYNC CONTROL) for managing the transfer of data within a system having a plurality of data sources (ASYNC BLOCK<1:n> asynchronous andor having different bitrates, to produce an output data stream (OUT) synchronous with a certain external timing signal (CLOCK, RD) of request of updating of the datum currently present at the output, comprising at least an output register (OUT REG) in which the datum to be made available at the output is stored and at least an output buffer (OUT BUFF) driving an external data line and functionally coupled to the output of said output register (OUT REG), each data source (ASYN_BLOCK<1:n>) having a data loading register (REG<1:n>), a selection multiplexer (MUX) of data to be transferred from one or another of said loading registers to said output register (OUT REG), a central control unit (CPU) producing a plurality of control signals (START<1:n>, REQ<1:n>, PRIORITY<i>, CLOCK, RD, GLOBAL RESET) according to a certain protocol, that are conveyed to said data sources (ASYNC BLOCK<1:n>) and to said circuit for managing the transfer, characterized in that said circuit for managing the transfer (SYNC_ASYN CONTROL) includes a plurality of identical circuits, each dedicated to one of said data sources and composed of:
a coincidence detecting circuit with hooking (COINCIDENCE DETECTOR WITH HOOKING) input with the logic end signal (PULSE) of said external timing signal (CLOCK RD) and of a selection signal (REQ<i>) of the source of the datum to be produced in output, and a confirmation signal (DATA_READY<i>) of availability of the datum at the output of said selected source, outputting in a stretching signal (OK_STR);
a conditioned update path of the output datum composed of:
a first bistable circuit (LATCH UPDATE FLAG) set by the inverted confirmation signal (DATA_READY<i>) and reset by the logic OR of a global reset command (GLOBAL_RESET) generated by the central control unit (CPU) and of the logic OR of the timing signal (CLOCK) and of the stretching signal (OK_STR), outputting a first flag (OK_UPDATE) of enablement of the updating;
a second bistable circuit (ENABLING FLAG OF OUT REG UPDATE) set by the output of said detecting circuit and reset by the logic OR of the signal (GLOBAL_RESET) and of a signal (NEW_OUT) corresponding to the logic OR of signals (NEW_OUT<i>) coming from the respective data sources <i>, outputting an update flag (PRE_LOAD);
a logic OR gate, input with the update flag (PRE-LOAD) and with the logic OR signal of the signal (PULSE) and of the stretching signal (OK_STR) and producing in output a selection signal (LOAD<i>) for the multiplexer (MUX);
a pass-gate coupling the input of an output buffer OUT BUFF to the respective output register OUT REG, enabled by the logic OR signal (NEW_OUT) of the signals (NEW_OUT<i>), each corresponding to the logic OR of the signal (PULSE) and of the stretching signal (OK_STR) of the managing circuit (block <i>) of a respective data source.
2. The circuit of claim 1, wherein the system further comprises a pulser circuit (PULSER) input with said external timing signal (RD) and outputting a pulse (LD_STIM) of preestablished duration at each rising edge of said external timing signal (RD);
said coincidence detector with hooking circuit (COINCIDENCE DETECTOR WITH HOOKING) receiving at an input the logic AND of said pulse of preestablished duration (LD_STIM) and of a selection signal (PRIORITY<i>) of the data source of the next datum to be output.
3. The circuit according to claim 2, wherein the system is an interleaved memory device and said asynchronous data sources are banks of subdivision of the memory cell array.