1. (canceled)
2. A method of treating type 1 diabetes in a subject, comprising:
administering a therapeutically effective dosage of an ATP signaling inhibitor to the subject.
3. The method of claim 2, wherein the inhibitor is a P2X7R signaling inhibitor.
4. The method of claim 2, wherein the inhibitor is a P2X7R-Ig fusion protein.
5. The method of claim 2, wherein the inhibitor is a P2X7R soluble protein.
6. The method of claim 2, wherein the inhibitor is a P2XR soluble protein.
7. The method of claim 2, wherein the inhibitor is a purinergic receptor inhibitor.
8. The method of claim 2, wherein the inhibitor is CE-224535, AZD9056, GSK1482160, or oATP.
9. The method of claim 2, wherein the inhibitor is an inhibitor of ATP exogenous to beta cells.
10. The method of claim 2, wherein the inhibitor is an ATPase on a cell surface.
11. The method of claim 10, wherein the cell is a T cell, nerve, dendritic or cardiomyocyte cell.
12. The method of claim 2, wherein the subject is human.
13. (canceled)
14. The method of claim 2, wherein the inhibitor degrades ATP.
15.-20. (canceled)
21. A composition, comprising:
a P2X7R-Ig fusion protein or a P2XR soluble protein; and
a pharmaceutically acceptable carrier.
22. The composition of claim 21, wherein the P2X7R-Ig fusion protein is a soluble protein with the ectodomain of a P2X7R receptor bound to the Fc portion of an IgG molecule.
23.-26. (canceled)
27. The composition of claim 22, wherein the fusion protein has the sequence of SEQ. ID. NO.: 1.
28.-40. (canceled)
41. A method of treating lung fibrosis in a subject, the method comprising administering a therapeutically effective dosage of an inhibitor of ATP signaling to the subject.
42.-49. (canceled)
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
What is claimed is:
1. A thin film transistor structure in which, on a substrate, formed are a source electrode; a drain electrode; a gate electrode; an active layer; a gate wiring connected to the gate electrode; and an insulating polymer film in which at least a trench is formed,
wherein said trench formed in said insulating polymer film accommodates said gate wiring constituted of a conductive layer, so that said gate wiring is self-aligned with said insulating polymer film.
2. The thin film transistor structure according to claim 1, wherein a thickness of said gate wiring is set to 2 micrometers to 15 micrometers, and an aspect ratio of said gate wiring ranges from 0.3 to 3.
3. The thin film transistor structure according to one of claims 1 and 2, wherein said insulating polymer film is subjected to a treatment for adjusting an optical property thereof.
4. The thin film transistor structure according to any one of claims 1 to 3, wherein said insulating polymer film includes a plurality of polymers.
5. The thin film transistor structure according to any one of claims 1 to 4, wherein said insulating polymer film includes a silicone-containing polymeric substance.
6. The thin film transistor structure according to any one of claims 1 to 5, wherein said gate wiring is constituted of the conductive layer forming a seed layer deposited by electroless plating and the conductive layer deposited by electroplating.
7. The thin film transistor structure according to any one of claims 1 to 6, wherein said thin film transistor is constituted as a bottom gate type thin film transistor or a top gate type thin film transistor.
8. The thin film transistor structure according to any one of claims 1 to 7, wherein said insulating polymer film comprises photosensitivity resin or photosensitive resin composition.
9. A method of manufacturing a thin film transistor structure in which, on a substrate, formed are a source electrode; a drain electrode; a gate electrode; an active layer; a gate wiring connected to said gate electrode; and an insulating polymer film in which at least a trench is formed, comprising the steps of:
forming the source electrode, the drain electrode, the gate electrode and the active layer;
forming the insulating polymer film on said substrate;
patterning said insulating polymer film to form the trench; and
depositing a conductive layer in said trench to form said gate wiring in self-alignment with said insulating polymer film.
10. The method according to claim 9, wherein said gate wiring is formed by the step of depositing a conductive layer forming a seed layer by use of electroless plating, and by the step of depositing a conductive layer different from said seed layer by use of electroplating.
11. The method according to claim 10, wherein the step of forming said gate wiring includes a step of controlling a current amount and a duration for said electroplating.
12. The method according to claim 10, wherein the step of forming said gate wiring includes: the step of forming, by use of the electroplating, the conductive layer different from the conductive layer to form said seed layer; and the step of making a level of the conductive layer formed by use of said electroplating equal to that of said insulating polymer film.
13. The method according to any one of claims 9 to 12, further comprising the step of subjecting said insulating polymer film to a treatment for adjusting an optical property thereof.
14. The method according to any one of claims 9 to 13, wherein said insulating polymer film contains a silicone-containing polymeric substance.
15. The method according to any one of claims 9 to 14, wherein said insulating polymer film is made of phtosensitive resin or photosensitive resin composition.
16. A display device including a thin film transistor structure in which, on a substrate, formed are a source electrode; a drain electrode; a gate electrode; an active layer; a gate wiring connected to said gate electrode; and an insulating polymer film in which at least a trench is formed, and said trench formed in said insulating polymer film accommodates said gate wiring constituted of a conductive layer so that said gate wiring is self-aligned with said insulating polymer film.
17. The display device according to claim 16, wherein a thickness of said gate wiring is set to 2 micrometers to 15 micrometers, and an aspect ratio of said gate electrode ranges from 0.3 to 3.
18. The display device according to one of claims 16 and 17, wherein said insulating polymer film is subjected to a treatment for adjusting an optical property thereof.
19. The display device according to any one of claims 16 to 18, wherein said insulating polymer film contains phtosensitive resin or photosensitive resin composition.
20. The display device according to any one of claims 16 to 19, wherein said insulating polymer film contains a silicone-containing polymeric substance.