1. A liquid crystal display (LCD) device comprising a TFT (thin-film-transistor) substrate mounting thereon a plurality of TFTS, a counter substrate mounting thereon a black matrix, a liquid crystal layer sandwiched between said TFT substrate and said counter substrate, and a backlight unit disposed at a rear side of said TFT substrate for irradiating said TFT substrate with backlight, each of said TFTs having a channel in a semiconductor layer, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.
2. The LCD device according to claim 1, wherein said channel length is larger at both edge portions of said channel than at said central portion thereof.
3. The LCD device according to claim 1, wherein said TFT includes a gate electrode disposed between said channel and said backlight unit, said gate electrode having a function of shielding said channel against said backlight.
4. The LCD device according to claim 1, wherein said semiconductor layer is made of an amorphous silicon film or a polysilicon film.
5. The LCD device according to claim 1, wherein said TFT includes source and drain electrodes opposing said gate electrode with an intervention of said semiconductor layer.
6. The LCD device according to claim 1, wherein said TFT includes an ohmic contact layer between said semiconductor layer and said source and drain electrodes.
7. The LCD device according to claim 1, wherein said source and drain electrodes of said TFT overlie said semiconductor layer.
8. A method for fabricating a TFT in an LCD device, comprising the steps of:
consecutively forming a gate electrode, a gate insulation film, a semiconductor layer and an ohmic contact layer of the TFT;
patterning said ohmic contact layer and said semiconductor layer;
forming a source electrode and a drain electrode of the TFT on said patterned ohmic contact layer; and
etching a portion of said patterned ohmic contact layer between said source electrode and said drain electrode by using said source electrode and said drain electrode as a mask to thereby expose a portion of said semiconductor layer as a channel, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.
9. A method for fabricating a TFT in an LCD device, comprising the steps of:
consecutively forming a gate electrode, a gate insulation film, a semiconductor layer and an ohmic contact layer of the TFT and a metallic film;
forming a photoresist film on said metallic film and exposing said photoresist film to exposure light having a specific wavelength through a photomask having a source electrode pattern, a drain electrode pattern and an intermediate pattern sandwiched between said source electrode pattern and said drain electrode pattern, said intermediate pattern having a width smaller than a limit of a resolution by said exposure light, to thereby form a photoresist mask pattern having a thickness larger at a region corresponding to said source and drain electrode patterns than at a region corresponding to a gap between said source electrode pattern and said drain electrode pattern;
patterning said metallic film, said ohmic contact layer and said semiconductor layer by using said photoresist mask pattern as a mask;
removing said photoresist mask pattern to leave a portion of said photoresist mask pattern having a specific thickness;
patterning said metallic film by using said portion of said photoresist mask pattern to form a source electrode and a drain electrode of the TFT; and
etching a portion of said patterned ohmic contact layer between said source electrode and said drain electrode by using said source electrode and said drain electrode as a mask to thereby expose a portion of said semiconductor layer as a channel, said channel having a channel length larger at an edge portion of said channel than at a central portion thereof.
10. The method according to claim 9, wherein said intermediate pattern is one or more slit pattern having said width smaller than said limit of resolution.
11. The method according to claim 9, wherein said intermediate pattern includes a plurality of stripe patterns arranged in an extending direction of said channel and each having dimensions smaller than said limit of resolution.
12. The method according to claim 9, wherein said intermediate pattern includes a plurality of dot patterns arranged in a matrix and having dimensions smaller than said limit of resolution.
13. The method according to claim 9, wherein said photoresist mask pattern removing step uses a reactive-ion-etching system.
14. The method according to claim 9, wherein said photoresist mask pattern removing step uses a UV ashing system.
15. The method according to claim 9, wherein said channel length is larger at both end portions of said channel than at said central portion thereof.
16. The method according to claim 9, wherein said semiconductor layer is made of an amorphous silicon film.
The claims below are in addition to those above.
All refrences to claim(s) which appear below refer to the numbering after this setence.
1. A storage controller, comprising:
a first inputoutput port that provides an interface to a host computer;
a second inputoutput port that provides an interface to a storage device;
a processor that receives inputoutput requests generated by the host computer and, in response to the inputoutput requests, generates and transmits inputoutput requests to the storage device; and
a memory module communicatively connected to the processor and comprising logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to:
receive, from the host computer, a write inputoutput request that identifies a logical volume;
compare an amount of storage space available in the logical volume with an amount of storage space required to complete the write operation; and
allocate additional storage space to the logical volume when the amount of storage space available in the logical volume is insufficient to complete the write operation.
2. The storage controller of claim 1, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to update meta data associated with the logical volume to reflect an allocation of additional storage space to the logical volume.
3. The storage controller of claim 1, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to dispatch the write operation to the logical volume
4. The storage controller of claim 1, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to compare an amount of storage space allocated to the logical volume with sum of the amount of data currently stored in the logical and the amount of data specified in the write operation.
5. A storage controller, comprising:
a first inputoutput port that provides an interface to a host computer;
a second inputoutput port that provides an interface to a storage device;
a processor that receives inputoutput requests generated by the host computer and, in response to the inputoutput requests, generates and transmits inputoutput requests to the storage device; and
a memory module communicatively connected to the processor and comprising logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to:
receive, from the host computer, a pre-allocate command that identifies a logical volume;
validate the pre-allocate command; and
allocate data from a free storage space to the logical volume identified in the pre-allocate command.
6. The storage controller of claim 5, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to validate the identity of the logical volume identified in the pre-allocate command.
7. The storage controller of claim 5, wherein:
the pre-allocate command specifies an amount of memory to pre-allocate to the logical volume; and
the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to verify that the free storage space includes sufficient space to allocate the amount of memory to the logical volume.
8. The storage controller of claim 5, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to transmit a response to a host computer when a specific bit is set in the pre-allocate command.
9. The storage controller of claim 5, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to update meta data associated with the logical volume to reflect an allocation of additional storage space to the logical volume.
10. The storage controller of claim 5, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to transmit a response to a host computer when the space is allocated to the logical volume.
11. A storage controller, comprising:
a first inputoutput port that provides an interface to a host computer;
a second inputoutput port that provides an interface to a storage device;
a processor that receives inputoutput requests generated by the host computer and, in response to the inputoutput requests, generates and transmits inputoutput requests to the storage device; and
a memory module communicatively connected to the processor and comprising logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to:
receive, from the host computer, a de-allocate command that identifies a logical volume;
validate the de-allocate command; and
de-allocate data from the logical volume identified in the de-allocate command.
12. The storage controller of claim 11, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to validate the identity of the logical volume identified in the de-allocate command.
13. The storage controller of claim 11, wherein:
the de-allocate command specifies an amount of memory to de-allocate from the logical volume; and
the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to verify that the logical volume includes sufficient space to de-allocate the amount from the logical volume.
14. The storage controller of claim 11, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to transmit a response to a host computer when a specific bit is set in the de-allocate command.
15. The storage controller of claim 11, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to update meta data associated with the logical volume to reflect a de-allocation of additional storage space to the logical volume.
16. The storage controller of claim 11, wherein the memory module further comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to transmit a response to a host computer when the space is de-allocated from the logical volume.